drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
Extension
.h
Size
8674 bytes
Lines
225
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef IPU6_PLATFORM_BUTTRESS_REGS_H
#define IPU6_PLATFORM_BUTTRESS_REGS_H

#include <linux/bits.h>

/* IS_WORKPOINT_REQ */
#define IPU6_BUTTRESS_REG_IS_FREQ_CTL		0x34
/* PS_WORKPOINT_REQ */
#define IPU6_BUTTRESS_REG_PS_FREQ_CTL		0x38

/* should be tuned for real silicon */
#define IPU6_IS_FREQ_CTL_DEFAULT_RATIO		0x08
#define IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO	0x0a
#define IPU6_PS_FREQ_CTL_DEFAULT_RATIO		0x0d

#define IPU6_IS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO	0x10
#define IPU6_PS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO	0x0708

#define IPU6_BUTTRESS_PWR_STATE_IS_PWR_SHIFT	3
#define IPU6_BUTTRESS_PWR_STATE_IS_PWR_MASK	GENMASK(4, 3)

#define IPU6_BUTTRESS_PWR_STATE_PS_PWR_SHIFT	6
#define IPU6_BUTTRESS_PWR_STATE_PS_PWR_MASK	GENMASK(7, 6)

#define IPU6_BUTTRESS_PWR_STATE_DN_DONE		0x0
#define IPU6_BUTTRESS_PWR_STATE_UP_PROCESS	0x1
#define IPU6_BUTTRESS_PWR_STATE_DN_PROCESS	0x2
#define IPU6_BUTTRESS_PWR_STATE_UP_DONE		0x3

#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_0	0x270
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_1	0x274
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_2	0x278
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_3	0x27c
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_4	0x280
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_5	0x284
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_6	0x288
#define IPU6_BUTTRESS_REG_FPGA_SUPPORT_7	0x28c

#define BUTTRESS_REG_WDT			0x8
#define BUTTRESS_REG_BTRS_CTRL			0xc
#define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC0	BIT(0)
#define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC1	BIT(1)
#define BUTTRESS_REG_BTRS_CTRL_REF_CLK_IND	GENMASK(9, 8)

#define BUTTRESS_REG_FW_RESET_CTL	0x30
#define BUTTRESS_FW_RESET_CTL_START	BIT(0)
#define BUTTRESS_FW_RESET_CTL_DONE	BIT(1)

#define BUTTRESS_REG_IS_FREQ_CTL	0x34
#define BUTTRESS_REG_PS_FREQ_CTL	0x38

#define BUTTRESS_FREQ_CTL_START		BIT(31)
#define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL		GENMASK(19, 16)
#define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK	GENMASK(15, 8)
#define BUTTRESS_FREQ_CTL_RATIO_MASK	GENMASK(7, 0)

#define BUTTRESS_REG_PWR_STATE	0x5c

#define BUTTRESS_PWR_STATE_RESET		0x0
#define BUTTRESS_PWR_STATE_PWR_ON_DONE		0x1
#define BUTTRESS_PWR_STATE_PWR_RDY		0x3
#define BUTTRESS_PWR_STATE_PWR_IDLE		0x4

#define BUTTRESS_PWR_STATE_HH_STATUS_MASK	GENMASK(12, 11)

enum {
	BUTTRESS_PWR_STATE_HH_STATE_IDLE,
	BUTTRESS_PWR_STATE_HH_STATE_IN_PRGS,
	BUTTRESS_PWR_STATE_HH_STATE_DONE,
	BUTTRESS_PWR_STATE_HH_STATE_ERR,
};

#define BUTTRESS_PWR_STATE_IS_PWR_FSM_MASK	GENMASK(23, 19)

#define BUTTRESS_PWR_STATE_IS_PWR_FSM_IDLE			0x0
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PLL_CMP		0x1
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK		0x2
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PG_ACK		0x3
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_ASSRT_CYCLES		0x4
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES1		0x5
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES2		0x6
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DEASSRT_CYCLES	0x7
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_FUSE_WR_CMP	0x8
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_BRK_POINT			0x9
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_IS_RDY			0xa
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_HALT_HALTED		0xb
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DURATION_CNT3		0xc
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK_PD		0xd
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_PD_BRK_POINT		0xe
#define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PD_PG_ACK0		0xf

Annotation

Implementation Notes