drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h
Extension
.h
Size
6136 bytes
Lines
173
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef IPU6_PLATFORM_ISYS_CSI2_REG_H
#define IPU6_PLATFORM_ISYS_CSI2_REG_H

#include <linux/bits.h>

#define CSI_REG_BASE			0x220000
#define CSI_REG_PORT_BASE(id)		(CSI_REG_BASE + (id) * 0x1000)

/* CSI Port Genral Purpose Registers */
#define CSI_REG_PORT_GPREG_SRST                 0x0
#define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST    0x4
#define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL    0x8

/*
 * Port IRQs mapping events:
 * IRQ0 - CSI_FE event
 * IRQ1 - CSI_SYNC
 * IRQ2 - S2M_SIDS0TO7
 * IRQ3 - S2M_SIDS8TO15
 */
#define CSI_PORT_REG_BASE_IRQ_CSI               0x80
#define CSI_PORT_REG_BASE_IRQ_CSI_SYNC          0xA0
#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7     0xC0
#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15    0xE0

#define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET	0x0
#define CSI_PORT_REG_BASE_IRQ_MASK_OFFSET	0x4
#define CSI_PORT_REG_BASE_IRQ_STATUS_OFFSET	0x8
#define CSI_PORT_REG_BASE_IRQ_CLEAR_OFFSET	0xc
#define CSI_PORT_REG_BASE_IRQ_ENABLE_OFFSET	0x10
#define CSI_PORT_REG_BASE_IRQ_LEVEL_NOT_PULSE_OFFSET	0x14

#define IPU6SE_CSI_RX_ERROR_IRQ_MASK		GENMASK(18, 0)
#define IPU6_CSI_RX_ERROR_IRQ_MASK		GENMASK(19, 0)

#define CSI_RX_NUM_ERRORS_IN_IRQ		20
#define CSI_RX_NUM_IRQ				32

#define IPU_CSI_RX_IRQ_FS_VC(chn)	(1 << ((chn) * 2))
#define IPU_CSI_RX_IRQ_FE_VC(chn)	(2 << ((chn) * 2))

/* PPI2CSI */
#define CSI_REG_PPI2CSI_ENABLE				0x200
#define CSI_REG_PPI2CSI_CONFIG_PPI_INTF			0x204
#define PPI_INTF_CONFIG_NOF_ENABLED_DLANES_MASK		GENMASK(4, 3)
#define CSI_REG_PPI2CSI_CONFIG_CSI_FEATURE		0x208

enum CSI_PPI2CSI_CTRL {
	CSI_PPI2CSI_DISABLE = 0,
	CSI_PPI2CSI_ENABLE = 1,
};

/* CSI_FE */
#define CSI_REG_CSI_FE_ENABLE                   0x280
#define CSI_REG_CSI_FE_MODE                     0x284
#define CSI_REG_CSI_FE_MUX_CTRL                 0x288
#define CSI_REG_CSI_FE_SYNC_CNTR_SEL            0x290

enum CSI_FE_ENABLE_TYPE {
	CSI_FE_DISABLE = 0,
	CSI_FE_ENABLE = 1,
};

enum CSI_FE_MODE_TYPE {
	CSI_FE_DPHY_MODE = 0,
	CSI_FE_CPHY_MODE = 1,
};

enum CSI_FE_INPUT_SELECTOR {
	CSI_SENSOR_INPUT = 0,
	CSI_MIPIGEN_INPUT = 1,
};

enum CSI_FE_SYNC_CNTR_SEL_TYPE {
	CSI_CNTR_SENSOR_LINE_ID = BIT(0),
	CSI_CNTR_INT_LINE_PKT_ID = ~CSI_CNTR_SENSOR_LINE_ID,
	CSI_CNTR_SENSOR_FRAME_ID = BIT(1),
	CSI_CNTR_INT_FRAME_PKT_ID = ~CSI_CNTR_SENSOR_FRAME_ID,
};

/* CSI HUB General Purpose Registers */
#define CSI_REG_HUB_GPREG_SRST			(CSI_REG_BASE + 0x18000)
#define CSI_REG_HUB_GPREG_SLV_REG_SRST		(CSI_REG_BASE + 0x18004)

#define CSI_REG_HUB_DRV_ACCESS_PORT(id)	(CSI_REG_BASE + 0x18018 + (id) * 4)
#define CSI_REG_HUB_FW_ACCESS_PORT_OFS		0x17000
#define CSI_REG_HUB_FW_ACCESS_PORT_V6OFS	0x16000
#define CSI_REG_HUB_FW_ACCESS_PORT(ofs, id)	\
					(CSI_REG_BASE + (ofs) + (id) * 4)

Annotation

Implementation Notes