drivers/media/pci/intel/ipu6/ipu6-platform-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/pci/intel/ipu6/ipu6-platform-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/intel/ipu6/ipu6-platform-regs.h
Extension
.h
Size
6825 bytes
Lines
180
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef IPU6_PLATFORM_REGS_H
#define IPU6_PLATFORM_REGS_H

#include <linux/bits.h>

/*
 * IPU6 uses uniform address within IPU6, therefore all subsystem registers
 * locates in one single space starts from 0 but in different sctions with
 * different addresses, the subsystem offsets are defined to 0 as the
 * register definition will have the address offset to 0.
 */
#define IPU6_UNIFIED_OFFSET			0

#define IPU6_ISYS_IOMMU0_OFFSET		0x2e0000
#define IPU6_ISYS_IOMMU1_OFFSET		0x2e0500
#define IPU6_ISYS_IOMMUI_OFFSET		0x2e0a00

#define IPU6_PSYS_IOMMU0_OFFSET		0x1b0000
#define IPU6_PSYS_IOMMU1_OFFSET		0x1b0700
#define IPU6_PSYS_IOMMU1R_OFFSET	0x1b0e00
#define IPU6_PSYS_IOMMUI_OFFSET		0x1b1500

/* the offset from IOMMU base register */
#define IPU6_MMU_L1_STREAM_ID_REG_OFFSET	0x0c
#define IPU6_MMU_L2_STREAM_ID_REG_OFFSET	0x4c
#define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET	0x8c

#define IPU6_MMU_INFO_OFFSET		0x8

#define IPU6_ISYS_SPC_OFFSET		0x210000

#define IPU6SE_PSYS_SPC_OFFSET		0x110000
#define IPU6_PSYS_SPC_OFFSET		0x118000

#define IPU6_ISYS_DMEM_OFFSET		0x200000
#define IPU6_PSYS_DMEM_OFFSET		0x100000

#define IPU6_REG_ISYS_UNISPART_IRQ_EDGE			0x27c000
#define IPU6_REG_ISYS_UNISPART_IRQ_MASK			0x27c004
#define IPU6_REG_ISYS_UNISPART_IRQ_STATUS		0x27c008
#define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR		0x27c00c
#define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE		0x27c010
#define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE	0x27c014
#define IPU6_REG_ISYS_UNISPART_SW_IRQ_REG		0x27c414
#define IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG		0x27c418
#define IPU6_ISYS_UNISPART_IRQ_CSI0			BIT(2)
#define IPU6_ISYS_UNISPART_IRQ_CSI1			BIT(3)
#define IPU6_ISYS_UNISPART_IRQ_SW			BIT(22)

#define IPU6_REG_ISYS_ISL_TOP_IRQ_EDGE			0x2b0200
#define IPU6_REG_ISYS_ISL_TOP_IRQ_MASK			0x2b0204
#define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS		0x2b0208
#define IPU6_REG_ISYS_ISL_TOP_IRQ_CLEAR			0x2b020c
#define IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE		0x2b0210
#define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE	0x2b0214

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE			0x2d2100
#define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK			0x2d2104
#define IPU6_REG_ISYS_CMPR_TOP_IRQ_STATUS		0x2d2108
#define IPU6_REG_ISYS_CMPR_TOP_IRQ_CLEAR		0x2d210c
#define IPU6_REG_ISYS_CMPR_TOP_IRQ_ENABLE		0x2d2110
#define IPU6_REG_ISYS_CMPR_TOP_IRQ_LEVEL_NOT_PULSE	0x2d2114

/* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */
#define IPU6_REG_ISYS_CDC_THRESHOLD(i)		(0x27c400 + ((i) * 4))

#define IPU6_CSI_IRQ_NUM_PER_PIPE			4
#define IPU6SE_ISYS_CSI_PORT_NUM			4
#define IPU6_ISYS_CSI_PORT_NUM				8

#define IPU6_ISYS_CSI_PORT_IRQ(irq_num)		BIT(irq_num)

/* PKG DIR OFFSET in IMR in secure mode */
#define IPU6_PKG_DIR_IMR_OFFSET			0x40

#define IPU6_ISYS_REG_SPC_STATUS_CTRL		0x0

#define IPU6_ISYS_SPC_STATUS_START			BIT(1)
#define IPU6_ISYS_SPC_STATUS_RUN			BIT(3)
#define IPU6_ISYS_SPC_STATUS_READY			BIT(5)
#define IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE	BIT(12)
#define IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH		BIT(13)

#define IPU6_PSYS_REG_SPC_STATUS_CTRL			0x0
#define IPU6_PSYS_REG_SPC_START_PC			0x4
#define IPU6_PSYS_REG_SPC_ICACHE_BASE			0x10
#define IPU6_REG_PSYS_INFO_SEG_0_CONFIG_ICACHE_MASTER	0x14

#define IPU6_PSYS_SPC_STATUS_START			BIT(1)
#define IPU6_PSYS_SPC_STATUS_RUN			BIT(3)

Annotation

Implementation Notes