drivers/media/pci/solo6x10/solo6x10-tw28.c

Source file repositories/reference/linux-study-clean/drivers/media/pci/solo6x10/solo6x10-tw28.c

File Facts

System
Linux kernel
Corpus path
drivers/media/pci/solo6x10/solo6x10-tw28.c
Extension
.c
Size
26080 bytes
Lines
870
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (i) {
		case 0xb8 ... 0xc1:
		case 0xc4 ... 0xc7:
		case 0xfd:
			continue;
		}
		switch (i & ~0x30) {
		case 0x00:
		case 0x0c ... 0x0d:
			continue;
		}

		tw_write_and_verify(solo_dev, dev_addr, i,
				    tbl_tw2865_common[i]);
	}

	return 0;
}

static int tw2864_setup(struct solo_dev *solo_dev, u8 dev_addr)
{
	u8 tbl_tw2864_common[256];
	int i;

	if (solo_dev->video_type == SOLO_VO_FMT_TYPE_PAL)
		memcpy(tbl_tw2864_common, tbl_tw2864_pal_template,
		       sizeof(tbl_tw2864_common));
	else
		memcpy(tbl_tw2864_common, tbl_tw2864_ntsc_template,
		       sizeof(tbl_tw2864_common));

	if (solo_dev->tw2865 == 0) {
		/* IRQ Mode */
		if (solo_dev->nr_chans == 4) {
			tbl_tw2864_common[0xd2] = 0x01;
			tbl_tw2864_common[0xcf] = 0x00;
		} else if (solo_dev->nr_chans == 8) {
			tbl_tw2864_common[0xd2] = 0x02;
			if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
				tbl_tw2864_common[0xcf] = 0x43;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
				tbl_tw2864_common[0xcf] = 0x40;
		} else if (solo_dev->nr_chans == 16) {
			tbl_tw2864_common[0xd2] = 0x03;
			if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
				tbl_tw2864_common[0xcf] = 0x43;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
				tbl_tw2864_common[0xcf] = 0x43;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
				tbl_tw2864_common[0xcf] = 0x43;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
				tbl_tw2864_common[0xcf] = 0x40;
		}
	} else {
		/* ALINK Mode. Assumes that the first tw28xx is a
		 * 2865 and these are in cascade. */
		for (i = 0; i <= 4; i++)
			tbl_tw2864_common[0x08 | i << 4] = 0x12;

		if (solo_dev->nr_chans == 8) {
			tbl_tw2864_common[0xd2] = 0x02;
			if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
				tbl_tw2864_common[0xcf] = 0x80;
		} else if (solo_dev->nr_chans == 16) {
			tbl_tw2864_common[0xd2] = 0x03;
			if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
				tbl_tw2864_common[0xcf] = 0x83;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
				tbl_tw2864_common[0xcf] = 0x83;
			else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
				tbl_tw2864_common[0xcf] = 0x80;
		}
	}

	for (i = 0; i < 0xff; i++) {
		/* Skip read only registers */
		switch (i) {
		case 0xb8 ... 0xc1:
		case 0xfd:
			continue;
		}
		switch (i & ~0x30) {
		case 0x00:
		case 0x0c:
		case 0x0d:
			continue;
		}

		tw_write_and_verify(solo_dev, dev_addr, i,
				    tbl_tw2864_common[i]);

Annotation

Implementation Notes