drivers/media/pci/tw5864/tw5864-reg.h
Source file repositories/reference/linux-study-clean/drivers/media/pci/tw5864/tw5864-reg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/pci/tw5864/tw5864-reg.h- Extension
.h- Size
- 65349 bytes
- Lines
- 2133
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#define TW5864_H264REV 0x0000
#define TW5864_EMU 0x0004
/* Define controls in register TW5864_EMU */
/* DDR controller enabled */
#define TW5864_EMU_EN_DDR BIT(0)
/* Enable bit for Inter module */
#define TW5864_EMU_EN_ME BIT(1)
/* Enable bit for Sensor Interface module */
#define TW5864_EMU_EN_SEN BIT(2)
/* Enable bit for Host Burst Access */
#define TW5864_EMU_EN_BHOST BIT(3)
/* Enable bit for Loop Filter module */
#define TW5864_EMU_EN_LPF BIT(4)
/* Enable bit for PLBK module */
#define TW5864_EMU_EN_PLBK BIT(5)
/*
* Video Frame mapping in DDR
* 00 CIF
* 01 D1
* 10 Reserved
* 11 Reserved
*
*/
#define TW5864_DSP_FRAME_TYPE (3 << 6)
#define TW5864_DSP_FRAME_TYPE_D1 BIT(6)
#define TW5864_UNDECLARED_H264REV_PART2 0x0008
#define TW5864_SLICE 0x000c
/* Define controls in register TW5864_SLICE */
/* VLC Slice end flag */
#define TW5864_VLC_SLICE_END BIT(0)
/* Master Slice End Flag */
#define TW5864_MAS_SLICE_END BIT(4)
/* Host to start a new slice Address */
#define TW5864_START_NSLICE BIT(15)
/*
* [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
* pointer for the last encoded frame of the corresponding channel.
*/
#define TW5864_ENC_BUF_PTR_REC1 0x0010
/* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
#define TW5864_DSP_QP 0x0018
/* Define controls in register TW5864_DSP_QP */
/* [5:0] H264 QP Value for codec */
#define TW5864_DSP_MB_QP 0x003f
/*
* [15:10] H264 LPF_OFFSET Address
* (Default 0)
*/
#define TW5864_DSP_LPF_OFFSET 0xfc00
#define TW5864_DSP_CODEC 0x001c
/* Define controls in register TW5864_DSP_CODEC */
/*
* 0: Encode (TW5864 Default)
* 1: Decode
*/
#define TW5864_DSP_CODEC_MODE BIT(0)
/*
* 0->3 4 VLC data buffer in DDR (1M each)
* 0->7 8 VLC data buffer in DDR (512k each)
*/
#define TW5864_VLC_BUF_ID (7 << 2)
/*
* 0 4CIF in 1 MB
* 1 1CIF in 1 MB
*/
#define TW5864_CIF_MAP_MD BIT(6)
/*
* 0 2 falf D1 in 1 MB
* 1 1 half D1 in 1 MB
*/
#define TW5864_HD1_MAP_MD BIT(7)
/* VLC Stream valid */
#define TW5864_VLC_VLD BIT(8)
/* MV Vector Valid */
#define TW5864_MV_VECT_VLD BIT(9)
/* MV Flag Valid */
#define TW5864_MV_FLAG_VLD BIT(10)
#define TW5864_DSP_SEN 0x0020
/* Define controls in register TW5864_DSP_SEN */
/* Org Buffer Base for Luma (default 0) */
#define TW5864_DSP_SEN_PIC_LU 0x000f
/* Org Buffer Base for Chroma (default 4) */
#define TW5864_DSP_SEN_PIC_CHM 0x00f0
Annotation
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.