drivers/media/platform/amlogic/c3/isp/c3-isp-core.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/amlogic/c3/isp/c3-isp-core.c

File Facts

System: Linux kernel
Corpus path: drivers/media/platform/amlogic/c3/isp/c3-isp-core.c
Extension: .c
Size: 19021 bytes
Lines: 642
Domain: Driver Families
Bucket: drivers/media
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/media/amlogic/c3-isp-config.h
linux/pm_runtime.h
media/v4l2-event.h
c3-isp-common.h
c3-isp-regs.h

Detected Declarations

struct c3_isp_core_format_info
function c3_isp_core_enable
function c3_isp_core_disable
function c3_isp_core_lswb_ofst
function c3_isp_core_3a_ofst
function c3_isp_core_dms_ofst
function c3_isp_core_cfg_format
function c3_isp_core_streams_ready
function for_each_media_entity_data_link
function c3_isp_core_enable_streams
function c3_isp_core_disable_streams
function c3_isp_core_enum_mbus_code
function c3_isp_core_set_sink_fmt
function c3_isp_core_set_source_fmt
function c3_isp_core_set_fmt
function c3_isp_core_init_state
function c3_isp_core_subscribe_event
function c3_isp_core_link_validate
function c3_isp_core_queue_sof
function c3_isp_core_register
function c3_isp_core_unregister

Annotated Snippet

struct c3_isp_core_format_info {
	u32 mbus_code;
	u32 pads;
	u8 xofst;
	u8 yofst;
	bool is_raw;
};

static const struct c3_isp_core_format_info c3_isp_core_fmts[] = {
	/* RAW formats */
	{
		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_0,
		.yofst		= C3_ISP_PHASE_OFFSET_1,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_1,
		.yofst		= C3_ISP_PHASE_OFFSET_1,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_0,
		.yofst		= C3_ISP_PHASE_OFFSET_0,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_1,
		.yofst		= C3_ISP_PHASE_OFFSET_0,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_0,
		.yofst		= C3_ISP_PHASE_OFFSET_1,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_1,
		.yofst		= C3_ISP_PHASE_OFFSET_1,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_0,
		.yofst		= C3_ISP_PHASE_OFFSET_0,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
		.pads		= BIT(C3_ISP_CORE_PAD_SINK_VIDEO),
		.xofst		= C3_ISP_PHASE_OFFSET_1,
		.yofst		= C3_ISP_PHASE_OFFSET_0,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SRGGB16_1X16,
		.pads		= BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_0)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_1)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_2),
		.xofst		= C3_ISP_PHASE_OFFSET_NONE,
		.yofst		= C3_ISP_PHASE_OFFSET_NONE,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SBGGR16_1X16,
		.pads		= BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_0)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_1)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_2),
		.xofst		= C3_ISP_PHASE_OFFSET_NONE,
		.yofst		= C3_ISP_PHASE_OFFSET_NONE,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGRBG16_1X16,
		.pads		= BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_0)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_1)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_2),
		.xofst		= C3_ISP_PHASE_OFFSET_NONE,
		.yofst		= C3_ISP_PHASE_OFFSET_NONE,
		.is_raw		= true,
	}, {
		.mbus_code	= MEDIA_BUS_FMT_SGBRG16_1X16,
		.pads		= BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_0)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_1)
				| BIT(C3_ISP_CORE_PAD_SOURCE_VIDEO_2),
		.xofst		= C3_ISP_PHASE_OFFSET_NONE,
		.yofst		= C3_ISP_PHASE_OFFSET_NONE,
		.is_raw		= true,

Annotation

Immediate include surface: `linux/media/amlogic/c3-isp-config.h`, `linux/pm_runtime.h`, `media/v4l2-event.h`, `c3-isp-common.h`, `c3-isp-regs.h`.
Detected declarations: `struct c3_isp_core_format_info`, `function c3_isp_core_enable`, `function c3_isp_core_disable`, `function c3_isp_core_lswb_ofst`, `function c3_isp_core_3a_ofst`, `function c3_isp_core_dms_ofst`, `function c3_isp_core_cfg_format`, `function c3_isp_core_streams_ready`, `function for_each_media_entity_data_link`, `function c3_isp_core_enable_streams`.
Atlas domain: Driver Families / drivers/media.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.