drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h
Extension
.h
Size
26603 bytes
Lines
619
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __C3_ISP_REGS_H__
#define __C3_ISP_REGS_H__

#define ISP_TOP_INPUT_SIZE				0x0000
#define ISP_TOP_INPUT_SIZE_VERT_SIZE_MASK		GENMASK(15, 0)
#define ISP_TOP_INPUT_SIZE_VERT_SIZE(x)			((x) << 0)
#define ISP_TOP_INPUT_SIZE_HORIZ_SIZE_MASK		GENMASK(31, 16)
#define ISP_TOP_INPUT_SIZE_HORIZ_SIZE(x)		((x) << 16)

#define ISP_TOP_FRM_SIZE				0x0004
#define ISP_TOP_FRM_SIZE_CORE_VERT_SIZE_MASK		GENMASK(15, 0)
#define ISP_TOP_FRM_SIZE_CORE_VERT_SIZE(x)		((x) << 0)
#define ISP_TOP_FRM_SIZE_CORE_HORIZ_SIZE_MASK		GENMASK(31, 16)
#define ISP_TOP_FRM_SIZE_CORE_HORIZ_SIZE(x)		((x) << 16)

#define ISP_TOP_HOLD_SIZE				0x0008
#define ISP_TOP_HOLD_SIZE_CORE_HORIZ_SIZE_MASK		GENMASK(31, 16)
#define ISP_TOP_HOLD_SIZE_CORE_HORIZ_SIZE(x)		((x) << 16)

#define ISP_TOP_PATH_EN					0x0010
#define ISP_TOP_PATH_EN_DISP0_EN_MASK			BIT(0)
#define ISP_TOP_PATH_EN_DISP0_EN			BIT(0)
#define ISP_TOP_PATH_EN_DISP0_DIS			(0 << 0)
#define ISP_TOP_PATH_EN_DISP1_EN_MASK			BIT(1)
#define ISP_TOP_PATH_EN_DISP1_EN			BIT(1)
#define ISP_TOP_PATH_EN_DISP1_DIS			(0 << 1)
#define ISP_TOP_PATH_EN_DISP2_EN_MASK			BIT(2)
#define ISP_TOP_PATH_EN_DISP2_EN			BIT(2)
#define ISP_TOP_PATH_EN_DISP2_DIS			(0 << 2)
#define ISP_TOP_PATH_EN_WRMIF0_EN_MASK			BIT(8)
#define ISP_TOP_PATH_EN_WRMIF0_EN			BIT(8)
#define ISP_TOP_PATH_EN_WRMIF0_DIS			(0 << 8)
#define ISP_TOP_PATH_EN_WRMIF1_EN_MASK			BIT(9)
#define ISP_TOP_PATH_EN_WRMIF1_EN			BIT(9)
#define ISP_TOP_PATH_EN_WRMIF1_DIS			(0 << 9)
#define ISP_TOP_PATH_EN_WRMIF2_EN_MASK			BIT(10)
#define ISP_TOP_PATH_EN_WRMIF2_EN			BIT(10)
#define ISP_TOP_PATH_EN_WRMIF2_DIS			(0 << 10)

#define ISP_TOP_PATH_SEL				0x0014
#define ISP_TOP_PATH_SEL_CORE_MASK			GENMASK(18, 16)
#define ISP_TOP_PATH_SEL_CORE_CORE_DIS			(0 << 16)
#define ISP_TOP_PATH_SEL_CORE_MIPI_CORE			BIT(16)

#define ISP_TOP_DISPIN_SEL				0x0018
#define ISP_TOP_DISPIN_SEL_DISP0_MASK			GENMASK(3, 0)
#define ISP_TOP_DISPIN_SEL_DISP0_CORE_OUT		(0 << 0)
#define ISP_TOP_DISPIN_SEL_DISP0_MIPI_OUT		(2 << 0)
#define ISP_TOP_DISPIN_SEL_DISP1_MASK			GENMASK(7, 4)
#define ISP_TOP_DISPIN_SEL_DISP1_CORE_OUT		(0 << 4)
#define ISP_TOP_DISPIN_SEL_DISP1_MIPI_OUT		(2 << 4)
#define ISP_TOP_DISPIN_SEL_DISP2_MASK			GENMASK(11, 8)
#define ISP_TOP_DISPIN_SEL_DISP2_CORE_OUT		(0 << 8)
#define ISP_TOP_DISPIN_SEL_DISP2_MIPI_OUT		(2 << 8)

#define ISP_TOP_IRQ_EN					0x0080
#define ISP_TOP_IRQ_EN_FRM_END_MASK			BIT(0)
#define ISP_TOP_IRQ_EN_FRM_END_EN			BIT(0)
#define ISP_TOP_IRQ_EN_FRM_END_DIS			(0 << 0)
#define ISP_TOP_IRQ_EN_FRM_RST_MASK			BIT(1)
#define ISP_TOP_IRQ_EN_FRM_RST_EN			BIT(1)
#define ISP_TOP_IRQ_EN_FRM_RST_DIS			(0 << 1)
#define ISP_TOP_IRQ_EN_3A_DMA_ERR_MASK			BIT(5)
#define ISP_TOP_IRQ_EN_3A_DMA_ERR_EN			BIT(5)
#define ISP_TOP_IRQ_EN_3A_DMA_ERR_DIS			(0 << 5)

#define ISP_TOP_IRQ_CLR					0x0084
#define ISP_TOP_RO_IRQ_STAT				0x01c4
#define ISP_TOP_RO_IRQ_STAT_FRM_END_MASK		BIT(0)
#define ISP_TOP_RO_IRQ_STAT_FRM_RST_MASK		BIT(1)
#define ISP_TOP_RO_IRQ_STAT_3A_DMA_ERR_MASK		BIT(5)

#define ISP_TOP_MODE_CTRL				0x0400
#define ISP_TOP_FEO_CTRL0				0x040c
#define ISP_TOP_FEO_CTRL0_INPUT_FMT_EN_MASK		BIT(8)
#define ISP_TOP_FEO_CTRL0_INPUT_FMT_DIS			(0 << 8)
#define ISP_TOP_FEO_CTRL0_INPUT_FMT_EN			BIT(8)

#define ISP_TOP_FEO_CTRL1_0				0x0410
#define ISP_TOP_FEO_CTRL1_0_DPC_EN_MASK			BIT(3)
#define ISP_TOP_FEO_CTRL1_0_DPC_DIS			(0 << 3)
#define ISP_TOP_FEO_CTRL1_0_DPC_EN			BIT(3)
#define ISP_TOP_FEO_CTRL1_0_OG_EN_MASK			BIT(5)
#define ISP_TOP_FEO_CTRL1_0_OG_DIS			(0 << 5)
#define ISP_TOP_FEO_CTRL1_0_OG_EN			BIT(5)

#define ISP_TOP_FED_CTRL				0x0418
#define ISP_TOP_FED_CTRL_PDPC_EN_MASK			BIT(1)
#define ISP_TOP_FED_CTRL_PDPC_DIS			(0 << 1)
#define ISP_TOP_FED_CTRL_PDPC_EN			BIT(1)

Annotation

Implementation Notes