drivers/media/platform/amphion/vpu_imx8q.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/amphion/vpu_imx8q.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/amphion/vpu_imx8q.c
Extension
.c
Size
6083 bytes
Lines
272
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vpu_sc_msg_misc {
	struct imx_sc_rpc_msg hdr;
	u32 word;
} __packed;
#endif

int vpu_imx8q_setup_dec(struct vpu_dev *vpu)
{
	const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;

	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f);
	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff);

	return 0;
}

int vpu_imx8q_setup_enc(struct vpu_dev *vpu)
{
	return 0;
}

int vpu_imx8q_setup(struct vpu_dev *vpu)
{
	const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;

	vpu_readl(vpu, offset + 0x108);

	vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1);
	vpu_writel(vpu, offset + 0x190, 0xffffffff);
	vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff);
	vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE);
	vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7);
	vpu_writel(vpu, XMEM_CONTROL, 0x102);

	vpu_readl(vpu, offset + 0x108);

	return 0;
}

static int vpu_imx8q_reset_enc(struct vpu_dev *vpu)
{
	return 0;
}

static int vpu_imx8q_reset_dec(struct vpu_dev *vpu)
{
	const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;

	vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff);

	return 0;
}

int vpu_imx8q_reset(struct vpu_dev *vpu)
{
	const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;

	vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7);
	vpu_imx8q_reset_enc(vpu);
	vpu_imx8q_reset_dec(vpu);

	return 0;
}

int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id)
{
	if (!config)
		return -EINVAL;

	switch (core_id) {
	case 0:
		config->malone_base_addr[0] = regs + DEC_MFD_XREG_SLV_BASE;
		config->num_malones = 1;
		config->num_windsors = 0;
		break;
	case 1:
		config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_0_BASE;
		config->num_windsors = 1;
		config->num_malones = 0;
		break;
	case 2:
		config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_1_BASE;
		config->num_windsors = 1;
		config->num_malones = 0;
		break;
	default:
		return -EINVAL;
	}
	if (config->num_windsors) {
		config->windsor_irq_pin[0x0][0x0] = WINDSOR_PAL_IRQ_PIN_L;

Annotation

Implementation Notes