drivers/media/platform/chips-media/wave5/wave5-regdefine.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/chips-media/wave5/wave5-regdefine.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/chips-media/wave5/wave5-regdefine.h
Extension
.h
Size
39959 bytes
Lines
738
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __WAVE5_REGISTER_DEFINE_H__
#define __WAVE5_REGISTER_DEFINE_H__

enum W5_VPU_COMMAND {
	W5_INIT_VPU		= 0x0001,
	W5_WAKEUP_VPU		= 0x0002,
	W5_SLEEP_VPU		= 0x0004,
	W5_CREATE_INSTANCE	= 0x0008,       /* queuing command */
	W5_FLUSH_INSTANCE	= 0x0010,
	W5_DESTROY_INSTANCE	= 0x0020,       /* queuing command */
	W5_INIT_SEQ		= 0x0040,       /* queuing command */
	W5_SET_FB		= 0x0080,
	W5_DEC_ENC_PIC		= 0x0100,       /* queuing command */
	W5_ENC_SET_PARAM	= 0x0200,	/* queuing command */
	W5_QUERY		= 0x4000,
	W5_UPDATE_BS		= 0x8000,
	W5_MAX_VPU_COMD		= 0x10000,
};

enum query_opt {
	GET_VPU_INFO		= 0,
	SET_WRITE_PROT		= 1,
	GET_RESULT		= 2,
	UPDATE_DISP_FLAG	= 3,
	GET_BW_REPORT		= 4,
	GET_BS_RD_PTR		= 5,		/* for decoder */
	GET_BS_WR_PTR		= 6,		/* for encoder */
	GET_SRC_BUF_FLAG	= 7,		/* for encoder */
	SET_BS_RD_PTR		= 8,		/* for decoder */
	GET_DEBUG_INFO		= 0x61,
};

#define W5_REG_BASE                     0x00000000
#define W5_CMD_REG_BASE                 0x00000100
#define W5_CMD_REG_END                  0x00000200

/*
 * COMMON
 *
 * ----
 *
 * Power on configuration
 * PO_DEBUG_MODE    [0]     1 - power on with debug mode
 * USE_PO_CONF      [3]     1 - use power-on-configuration
 */
#define W5_PO_CONF                     (W5_REG_BASE + 0x0000)
#define W5_VCPU_CUR_PC                 (W5_REG_BASE + 0x0004)
#define W5_VCPU_CUR_LR                 (W5_REG_BASE + 0x0008)
#define W5_VPU_PDBG_STEP_MASK_V        (W5_REG_BASE + 0x000C)
#define W5_VPU_PDBG_CTRL               (W5_REG_BASE + 0x0010) /* v_cpu debugger ctrl register */
#define W5_VPU_PDBG_IDX_REG            (W5_REG_BASE + 0x0014) /* v_cpu debugger index register */
#define W5_VPU_PDBG_WDATA_REG          (W5_REG_BASE + 0x0018) /* v_cpu debugger write data reg */
#define W5_VPU_PDBG_RDATA_REG          (W5_REG_BASE + 0x001C) /* v_cpu debugger read data reg */

#define W5_VPU_FIO_CTRL_ADDR           (W5_REG_BASE + 0x0020)
#define W5_VPU_FIO_DATA                (W5_REG_BASE + 0x0024)
#define W5_VPU_VINT_REASON_USR         (W5_REG_BASE + 0x0030)
#define W5_VPU_VINT_REASON_CLR         (W5_REG_BASE + 0x0034)
#define W5_VPU_HOST_INT_REQ            (W5_REG_BASE + 0x0038)
#define W5_VPU_VINT_CLEAR              (W5_REG_BASE + 0x003C)
#define W5_VPU_HINT_CLEAR              (W5_REG_BASE + 0x0040)
#define W5_VPU_VPU_INT_STS             (W5_REG_BASE + 0x0044)
#define W5_VPU_VINT_ENABLE             (W5_REG_BASE + 0x0048)
#define W5_VPU_VINT_REASON             (W5_REG_BASE + 0x004C)
#define W5_VPU_RESET_REQ               (W5_REG_BASE + 0x0050)
#define W5_RST_BLOCK_CCLK(_core)       BIT((_core))
#define W5_RST_BLOCK_CCLK_ALL          (0xff)
#define W5_RST_BLOCK_BCLK(_core)       (0x100 << (_core))
#define W5_RST_BLOCK_BCLK_ALL          (0xff00)
#define W5_RST_BLOCK_ACLK(_core)       (0x10000 << (_core))
#define W5_RST_BLOCK_ACLK_ALL          (0xff0000)
#define W5_RST_BLOCK_VCPU_ALL          (0x3f000000)
#define W5_RST_BLOCK_ALL               (0x3fffffff)
#define W5_VPU_RESET_STATUS            (W5_REG_BASE + 0x0054)

#define W5_VCPU_RESTART                (W5_REG_BASE + 0x0058)
#define W5_VPU_CLK_MASK                (W5_REG_BASE + 0x005C)

/* REMAP_CTRL
 * PAGE SIZE:   [8:0]   0x001 - 4K
 *                      0x002 - 8K
 *                      0x004 - 16K
 *                      ...
 *                      0x100 - 1M
 * REGION ATTR1 [10]    0     - normal
 *                      1     - make bus error for the region
 * REGION ATTR2 [11]    0     - normal
 *                      1     - bypass region
 * REMAP INDEX  [15:12]       - 0 ~ 3
 * ENDIAN       [19:16]       - NOTE: Currently not supported in this driver

Annotation

Implementation Notes