drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
Source file repositories/reference/linux-study-clean/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c- Extension
.c- Size
- 59058 bytes
- Lines
- 2029
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pm_runtime.hwave5-helper.h
Detected Declarations
function switch_statefunction set_instance_statefunction wave5_vpu_dec_set_eos_on_firmwarefunction wave5_last_src_buffer_consumedfunction wave5_handle_src_bufferfunction v4l2_m2m_for_each_src_buf_safefunction start_decodefunction flag_last_buffer_donefunction send_eos_eventfunction wave5_update_min_bufs_ctrlfunction handle_dynamic_resolution_changefunction wave5_vpu_dec_finish_decodefunction wave5_vpu_dec_querycapfunction wave5_vpu_dec_enum_framesizesfunction wave5_vpu_dec_enum_fmt_capfunction wave5_vpu_dec_try_fmt_capfunction wave5_vpu_dec_s_fmt_capfunction wave5_vpu_dec_g_fmt_capfunction wave5_vpu_dec_enum_fmt_outfunction wave5_vpu_dec_try_fmt_outfunction wave5_vpu_dec_s_fmt_outfunction wave5_vpu_dec_g_selectionfunction wave5_vpu_dec_s_selectionfunction wave5_vpu_dec_stopfunction wave5_vpu_dec_startfunction wave5_vpu_dec_decoder_cmdfunction wave5_vpu_dec_queue_setupfunction wave5_prepare_fbfunction v4l2_m2m_for_each_dst_buf_safefunction write_to_ringbufferfunction fill_ringbufferfunction wave5_vpu_dec_buf_queue_srcfunction wave5_vpu_dec_buf_queue_dstfunction wave5_vpu_dec_buf_queuefunction wave5_vpu_dec_allocate_ring_bufferfunction wave5_vpu_dec_start_streamingfunction streamoff_outputfunction streamoff_capturefunction wave5_vpu_dec_stop_streamingfunction wave5_set_default_formatfunction wave5_vpu_dec_queue_initfunction initialize_sequencefunction wave5_is_draining_or_eosfunction wave5_vpu_dec_device_runfunction wave5_vpu_dec_job_abortfunction wave5_vpu_dec_job_readyfunction wave5_vpu_open_decfunction wave5_vpu_dec_release
Annotated Snippet
if (src_buf == m2m_ctx->last_src_buf) {
int ret;
m2m_ctx->last_src_buf = NULL;
ret = wave5_vpu_dec_set_eos_on_firmware(inst);
if (ret)
dev_warn(inst->dev->dev,
"Setting EOS for the bitstream, fail: %d\n", ret);
break;
}
}
inst->remaining_consumed_bytes = consumed_bytes;
}
static int start_decode(struct vpu_instance *inst, u32 *fail_res)
{
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
int ret = 0;
ret = wave5_vpu_dec_start_one_frame(inst, fail_res);
if (ret) {
struct vb2_v4l2_buffer *src_buf;
src_buf = v4l2_m2m_src_buf_remove(m2m_ctx);
if (src_buf)
v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
set_instance_state(inst, VPU_INST_STATE_STOP);
dev_dbg(inst->dev->dev, "%s: pic run failed / finish job", __func__);
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
}
return ret;
}
static void flag_last_buffer_done(struct vpu_instance *inst)
{
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
struct vb2_v4l2_buffer *vb;
int i;
lockdep_assert_held(&inst->state_spinlock);
vb = v4l2_m2m_dst_buf_remove(m2m_ctx);
if (!vb) {
m2m_ctx->is_draining = true;
m2m_ctx->next_buf_last = true;
return;
}
for (i = 0; i < vb->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&vb->vb2_buf, i, 0);
vb->field = V4L2_FIELD_NONE;
v4l2_m2m_last_buffer_done(m2m_ctx, vb);
}
static void send_eos_event(struct vpu_instance *inst)
{
static const struct v4l2_event vpu_event_eos = {
.type = V4L2_EVENT_EOS
};
lockdep_assert_held(&inst->state_spinlock);
v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos);
inst->eos = false;
inst->sent_eos = true;
}
static void wave5_update_min_bufs_ctrl(struct vpu_instance *inst, u32 fbc_buf_count)
{
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
struct v4l2_ctrl *ctrl;
if (!fbc_buf_count || fbc_buf_count == v4l2_m2m_num_dst_bufs_ready(m2m_ctx))
return;
ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl,
V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);
if (ctrl)
v4l2_ctrl_s_ctrl(ctrl, fbc_buf_count);
}
static int handle_dynamic_resolution_change(struct vpu_instance *inst)
{
struct v4l2_fh *fh = &inst->v4l2_fh;
static const struct v4l2_event vpu_event_src_ch = {
Annotation
- Immediate include surface: `linux/pm_runtime.h`, `wave5-helper.h`.
- Detected declarations: `function switch_state`, `function set_instance_state`, `function wave5_vpu_dec_set_eos_on_firmware`, `function wave5_last_src_buffer_consumed`, `function wave5_handle_src_buffer`, `function v4l2_m2m_for_each_src_buf_safe`, `function start_decode`, `function flag_last_buffer_done`, `function send_eos_event`, `function wave5_update_min_bufs_ctrl`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.