drivers/media/platform/chips-media/wave5/wave5-vpu.h
Source file repositories/reference/linux-study-clean/drivers/media/platform/chips-media/wave5/wave5-vpu.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/chips-media/wave5/wave5-vpu.h- Extension
.h- Size
- 2383 bytes
- Lines
- 86
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
media/v4l2-ctrls.hmedia/v4l2-ioctl.hmedia/v4l2-event.hmedia/v4l2-fh.hmedia/videobuf2-v4l2.hmedia/videobuf2-dma-contig.hmedia/videobuf2-vmalloc.hwave5-vpuconfig.hwave5-vpuapi.h
Detected Declarations
struct vpu_src_bufferstruct vpu_dst_bufferstruct vpu_formatenum vpu_fmt_typefunction wave5_vpu_both_queues_are_streaming
Annotated Snippet
struct vpu_src_buffer {
struct v4l2_m2m_buffer v4l2_m2m_buf;
bool consumed;
struct list_head list;
};
struct vpu_dst_buffer {
struct v4l2_m2m_buffer v4l2_m2m_buf;
bool display;
};
enum vpu_fmt_type {
VPU_FMT_TYPE_CODEC = 0,
VPU_FMT_TYPE_RAW = 1
};
struct vpu_format {
unsigned int v4l2_pix_fmt;
const struct v4l2_frmsize_stepwise *v4l2_frmsize;
};
static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh)
{
return container_of(vfh, struct vpu_instance, v4l2_fh);
}
static inline struct vpu_instance *file_to_vpu_inst(struct file *filp)
{
return wave5_to_vpu_inst(file_to_v4l2_fh(filp));
}
static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl)
{
return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl);
}
static inline struct vpu_src_buffer *wave5_to_vpu_src_buf(struct vb2_v4l2_buffer *vbuf)
{
return container_of(vbuf, struct vpu_src_buffer, v4l2_m2m_buf.vb);
}
static inline struct vpu_dst_buffer *wave5_to_vpu_dst_buf(struct vb2_v4l2_buffer *vbuf)
{
return container_of(vbuf, struct vpu_dst_buffer, v4l2_m2m_buf.vb);
}
int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout);
int wave5_vpu_dec_register_device(struct vpu_device *dev);
void wave5_vpu_dec_unregister_device(struct vpu_device *dev);
int wave5_vpu_enc_register_device(struct vpu_device *dev);
void wave5_vpu_enc_unregister_device(struct vpu_device *dev);
static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst)
{
struct vb2_queue *vq_cap =
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
struct vb2_queue *vq_out =
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out);
}
#endif
Annotation
- Immediate include surface: `media/v4l2-ctrls.h`, `media/v4l2-ioctl.h`, `media/v4l2-event.h`, `media/v4l2-fh.h`, `media/videobuf2-v4l2.h`, `media/videobuf2-dma-contig.h`, `media/videobuf2-vmalloc.h`, `wave5-vpuconfig.h`.
- Detected declarations: `struct vpu_src_buffer`, `struct vpu_dst_buffer`, `struct vpu_format`, `enum vpu_fmt_type`, `function wave5_vpu_both_queues_are_streaming`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.