drivers/media/platform/chips-media/wave5/wave5-vpuerror.h

File Facts

System

Linux kernel

Corpus path

drivers/media/platform/chips-media/wave5/wave5-vpuerror.h

Extension

.h

Size

21804 bytes

Lines

293

Domain

Driver Families

Bucket

drivers/media

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ERROR_CODE_H_INCLUDED
#define ERROR_CODE_H_INCLUDED

/*
 * WAVE5
 */

/************************************************************************/
/* WAVE5 COMMON SYSTEM ERROR (FAIL_REASON)                              */
/************************************************************************/
#define WAVE5_SYSERR_QUEUEING_FAIL                                     0x00000001
#define WAVE5_SYSERR_ACCESS_VIOLATION_HW                               0x00000040
#define WAVE5_SYSERR_BUS_ERROR                                         0x00000200
#define WAVE5_SYSERR_DOUBLE_FAULT                                      0x00000400
#define WAVE5_SYSERR_RESULT_NOT_READY                                  0x00000800
#define WAVE5_SYSERR_VPU_STILL_RUNNING                                 0x00001000
#define WAVE5_SYSERR_UNKNOWN_CMD                                       0x00002000
#define WAVE5_SYSERR_UNKNOWN_CODEC_STD                                 0x00004000
#define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION                              0x00008000
#define WAVE5_SYSERR_VLC_BUF_FULL                                      0x00010000
#define WAVE5_SYSERR_WATCHDOG_TIMEOUT                                  0x00020000
#define WAVE5_SYSERR_VCPU_TIMEOUT                                      0x00080000
#define WAVE5_SYSERR_TEMP_SEC_BUF_OVERFLOW                             0x00200000
#define WAVE5_SYSERR_NEED_MORE_TASK_BUF                                0x00400000
#define WAVE5_SYSERR_PRESCAN_ERR                                       0x00800000
#define WAVE5_SYSERR_ENC_GBIN_OVERCONSUME                              0x01000000
#define WAVE5_SYSERR_ENC_MAX_ZERO_DETECT                               0x02000000
#define WAVE5_SYSERR_ENC_LVL_FIRST_ERROR                               0x04000000
#define WAVE5_SYSERR_ENC_EG_RANGE_OVER                                 0x08000000
#define WAVE5_SYSERR_ENC_IRB_FRAME_DROP                                0x10000000
#define WAVE5_SYSERR_INPLACE_V                                         0x20000000
#define WAVE5_SYSERR_FATAL_VPU_HANGUP                                  0xf0000000

/************************************************************************/
/* WAVE5 COMMAND QUEUE ERROR (FAIL_REASON)                              */
/************************************************************************/
#define WAVE5_CMDQ_ERR_NOT_QUEABLE_CMD                                 0x00000001
#define WAVE5_CMDQ_ERR_SKIP_MODE_ENABLE                                0x00000002
#define WAVE5_CMDQ_ERR_INST_FLUSHING                                   0x00000003
#define WAVE5_CMDQ_ERR_INST_INACTIVE                                   0x00000004
#define WAVE5_CMDQ_ERR_QUEUE_FAIL                                      0x00000005
#define WAVE5_CMDQ_ERR_CMD_BUF_FULL                                    0x00000006

/************************************************************************/
/* WAVE5 ERROR ON DECODER (ERR_INFO)                                    */
/************************************************************************/
// HEVC
#define HEVC_SPSERR_SEQ_PARAMETER_SET_ID                               0x00001000
#define HEVC_SPSERR_CHROMA_FORMAT_IDC                                  0x00001001
#define HEVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES                          0x00001002
#define HEVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES                         0x00001003
#define HEVC_SPSERR_CONF_WIN_LEFT_OFFSET                               0x00001004
#define HEVC_SPSERR_CONF_WIN_RIGHT_OFFSET                              0x00001005
#define HEVC_SPSERR_CONF_WIN_TOP_OFFSET                                0x00001006
#define HEVC_SPSERR_CONF_WIN_BOTTOM_OFFSET                             0x00001007
#define HEVC_SPSERR_BIT_DEPTH_LUMA_MINUS8                              0x00001008
#define HEVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8                            0x00001009
#define HEVC_SPSERR_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4                  0x0000100A
#define HEVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING                          0x0000100B
#define HEVC_SPSERR_SPS_MAX_NUM_REORDER_PICS                           0x0000100C
#define HEVC_SPSERR_SPS_MAX_LATENCY_INCREASE                           0x0000100D
#define HEVC_SPSERR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3             0x0000100E
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE           0x0000100F
#define HEVC_SPSERR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2               0x00001010
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE             0x00001011
#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER                0x00001012
#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA                0x00001013
#define HEVC_SPSERR_SCALING_LIST                                       0x00001014
#define HEVC_SPSERR_LOG2_DIFF_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3    0x00001015
#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE       0x00001016
#define HEVC_SPSERR_NUM_SHORT_TERM_REF_PIC_SETS                        0x00001017
#define HEVC_SPSERR_NUM_LONG_TERM_REF_PICS_SPS                         0x00001018
#define HEVC_SPSERR_GBU_PARSING_ERROR                                  0x00001019
#define HEVC_SPSERR_EXTENSION_FLAG                                     0x0000101A
#define HEVC_SPSERR_VUI_ERROR                                          0x0000101B
#define HEVC_SPSERR_ACTIVATE_SPS                                       0x0000101C
#define HEVC_SPSERR_PROFILE_SPACE                                      0x0000101D
#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID                           0x00002000
#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID                           0x00002001
#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1               0x00002002
#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1               0x00002003
#define HEVC_PPSERR_INIT_QP_MINUS26                                    0x00002004
#define HEVC_PPSERR_DIFF_CU_QP_DELTA_DEPTH                             0x00002005
#define HEVC_PPSERR_PPS_CB_QP_OFFSET                                   0x00002006
#define HEVC_PPSERR_PPS_CR_QP_OFFSET                                   0x00002007
#define HEVC_PPSERR_NUM_TILE_COLUMNS_MINUS1                            0x00002008
#define HEVC_PPSERR_NUM_TILE_ROWS_MINUS1                               0x00002009
#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1                                0x0000200A
#define HEVC_PPSERR_ROW_HEIGHT_MINUS1                                  0x0000200B
#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2                               0x0000200C

Annotation

• Atlas domain: Driver Families / drivers/media.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.