drivers/media/platform/imagination/e5010-jpeg-enc-hw.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/imagination/e5010-jpeg-enc-hw.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/imagination/e5010-jpeg-enc-hw.c
Extension
.c
Size
8183 bytes
Lines
268
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Imagination E5010 JPEG Encoder driver.
 *
 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Author: David Huang <d-huang@ti.com>
 * Author: Devarsh Thakkar <devarsht@ti.com>
 */

#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/dev_printk.h>
#include "e5010-jpeg-enc-hw.h"

static void write_reg_field(void __iomem *base, unsigned int offset, u32 mask,
			    unsigned int shift, u32 value)
{
	u32 reg;

	value <<= shift;
	if (mask != 0xffffffff) {
		reg = readl(base + offset);
		value = (value & mask) | (reg & ~mask);
	}
	writel(value, (base + offset));
}

static int write_reg_field_not_busy(void __iomem *jasper_base, void __iomem *wr_base,
				    unsigned int offset, u32 mask, unsigned int shift,
				    u32 value)
{
	int ret;
	u32 val;

	ret = readl_poll_timeout_atomic(jasper_base + JASPER_STATUS_OFFSET, val,
					(val & JASPER_STATUS_CR_JASPER_BUSY_MASK) == 0,
					2000, 50000);
	if (ret)
		return ret;

	write_reg_field(wr_base, offset, mask, shift, value);

	return 0;
}

void e5010_reset(struct device *dev, void __iomem *core_base, void __iomem *mmu_base)
{
	int ret = 0;
	u32 val;

	write_reg_field(core_base, JASPER_RESET_OFFSET,
			JASPER_RESET_CR_CORE_RESET_MASK,
			JASPER_RESET_CR_CORE_RESET_SHIFT, 1);

	write_reg_field(mmu_base, MMU_MMU_CONTROL1_OFFSET,
			MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK,
			MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT, 1);

	ret = readl_poll_timeout_atomic(mmu_base + MMU_MMU_CONTROL1_OFFSET, val,
					(val & MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK) == 0,
					2000, 50000);
	if (ret)
		dev_warn(dev, "MMU soft reset timed out, forcing system soft reset\n");

	write_reg_field(core_base, JASPER_RESET_OFFSET,
			JASPER_RESET_CR_SYS_RESET_MASK,
			JASPER_RESET_CR_SYS_RESET_SHIFT, 1);
}

void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable)
{
	/* Bypass MMU */
	write_reg_field(mmu_base,
			MMU_MMU_ADDRESS_CONTROL_OFFSET,
			MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK,
			MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT,
			enable);
}

int e5010_hw_enable_output_address_error_irq(void __iomem *core_base, u32 enable)
{
	return write_reg_field_not_busy(core_base, core_base,
				       JASPER_INTERRUPT_MASK_OFFSET,
				       JASPER_INTERRUPT_MASK_CR_OUTPUT_ADDRESS_ERROR_ENABLE_MASK,
				       JASPER_INTERRUPT_MASK_CR_OUTPUT_ADDRESS_ERROR_ENABLE_SHIFT,
				       enable);
}

bool e5010_hw_pic_done_irq(void __iomem *core_base)

Annotation

Implementation Notes