drivers/media/platform/imagination/e5010-mmu-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/imagination/e5010-mmu-regs.h

File Facts

System: Linux kernel
Corpus path: drivers/media/platform/imagination/e5010-mmu-regs.h
Extension: .h
Size: 11585 bytes
Lines: 312
Domain: Driver Families
Bucket: drivers/media
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _E5010_MMU_REGS_H
#define _E5010_MMU_REGS_H

#define MMU_MMU_DIR_BASE_ADDR_OFFSET					(0x0020)
#define MMU_MMU_DIR_BASE_ADDR_STRIDE					(4)
#define MMU_MMU_DIR_BASE_ADDR_NO_ENTRIES				(4)

#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK			(0xFFFFFFFF)
#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT			(0)

#define MMU_MMU_TILE_CFG_OFFSET						(0x0040)
#define MMU_MMU_TILE_CFG_STRIDE						(4)
#define MMU_MMU_TILE_CFG_NO_ENTRIES					(4)

#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK			(0x00000010)
#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_SHIFT			(4)

#define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK				(0x00000008)
#define MMU_MMU_TILE_CFG_TILE_ENABLE_SHIFT				(3)

#define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK				(0x00000007)
#define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT				(0)

#define MMU_MMU_TILE_MIN_ADDR_OFFSET					(0x0050)
#define MMU_MMU_TILE_MIN_ADDR_STRIDE					(4)
#define MMU_MMU_TILE_MIN_ADDR_NO_ENTRIES				(4)

#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK			(0xFFFFFFFF)
#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_SHIFT			(0)

#define MMU_MMU_TILE_MAX_ADDR_OFFSET					(0x0060)
#define MMU_MMU_TILE_MAX_ADDR_STRIDE					(4)
#define MMU_MMU_TILE_MAX_ADDR_NO_ENTRIES				(4)

#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_MASK			(0xFFFFFFFF)
#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_SHIFT			(0)

#define MMU_MMU_CONTROL0_OFFSET						(0x0000)

#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_MASK				(0x00000001)
#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_SHIFT			(0)

#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_MASK				(0x00000100)
#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_SHIFT				(8)

#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_MASK			(0x00000200)
#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_SHIFT		(9)

#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_MASK			(0x00001000)
#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_SHIFT			(12)

#define MMU_MMU_CONTROL1_OFFSET						(0x0008)

#define MMU_MMU_CONTROL1_MMU_FLUSH_MASK					(0x00000008)
#define MMU_MMU_CONTROL1_MMU_FLUSH_SHIFT				(3)
#define MMU_MMU_CONTROL1_MMU_FLUSH_NO_REPS				(4)
#define MMU_MMU_CONTROL1_MMU_FLUSH_SIZE					(1)

#define MMU_MMU_CONTROL1_MMU_INVALDC_MASK				(0x00000800)
#define MMU_MMU_CONTROL1_MMU_INVALDC_SHIFT				(11)
#define MMU_MMU_CONTROL1_MMU_INVALDC_NO_REPS				(4)
#define MMU_MMU_CONTROL1_MMU_INVALDC_SIZE				(1)

#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_MASK				(0x00010000)
#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_SHIFT				(16)

#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_MASK			(0x00100000)
#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_SHIFT			(20)

#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_MASK				(0x01000000)
#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_SHIFT				(24)

#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_MASK				(0x02000000)
#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_SHIFT				(25)

#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK				(0x10000000)
#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT				(28)

#define MMU_MMU_BANK_INDEX_OFFSET					(0x0010)

#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_MASK				(0xC0000000)
#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SHIFT				(30)
#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_NO_REPS			(16)
#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SIZE				(2)

#define MMU_REQUEST_PRIORITY_ENABLE_OFFSET				(0x0018)

#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_MASK		(0x00008000)
#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SHIFT		(15)
#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_NO_REPS		(16)

Annotation

Atlas domain: Driver Families / drivers/media.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.