drivers/media/platform/microchip/microchip-isc-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/microchip/microchip-isc-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/microchip/microchip-isc-regs.h
Extension
.h
Size
12126 bytes
Lines
414
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MICROCHIP_ISC_REGS_H
#define __MICROCHIP_ISC_REGS_H

#include <linux/bitops.h>

/* ISC Control Enable Register 0 */
#define ISC_CTRLEN      0x00000000

/* ISC Control Disable Register 0 */
#define ISC_CTRLDIS     0x00000004

/* ISC Control Status Register 0 */
#define ISC_CTRLSR      0x00000008

#define ISC_CTRL_CAPTURE	BIT(0)
#define ISC_CTRL_UPPRO		BIT(1)
#define ISC_CTRL_HISREQ		BIT(2)
#define ISC_CTRL_HISCLR		BIT(3)

/* ISC Parallel Front End Configuration 0 Register */
#define ISC_PFE_CFG0    0x0000000c

#define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
#define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
#define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
#define ISC_PFE_CFG0_CCIR656    BIT(9)
#define ISC_PFE_CFG0_CCIR_CRC   BIT(10)
#define ISC_PFE_CFG0_MIPI	BIT(14)

#define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
#define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)

#define ISC_PFE_CFG0_BPS_EIGHT  (0x4 << 28)
#define ISC_PFG_CFG0_BPS_NINE   (0x3 << 28)
#define ISC_PFG_CFG0_BPS_TEN    (0x2 << 28)
#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
#define ISC_PFE_CFG0_BPS_MASK   GENMASK(30, 28)

#define ISC_PFE_CFG0_COLEN	BIT(12)
#define ISC_PFE_CFG0_ROWEN	BIT(13)

/* ISC Parallel Front End Configuration 1 Register */
#define ISC_PFE_CFG1    0x00000010

#define ISC_PFE_CFG1_COLMIN(v)		((v))
#define ISC_PFE_CFG1_COLMIN_MASK	GENMASK(15, 0)
#define ISC_PFE_CFG1_COLMAX(v)		((v) << 16)
#define ISC_PFE_CFG1_COLMAX_MASK	GENMASK(31, 16)

/* ISC Parallel Front End Configuration 2 Register */
#define ISC_PFE_CFG2    0x00000014

#define ISC_PFE_CFG2_ROWMIN(v)		((v))
#define ISC_PFE_CFG2_ROWMIN_MASK	GENMASK(15, 0)
#define ISC_PFE_CFG2_ROWMAX(v)		((v) << 16)
#define ISC_PFE_CFG2_ROWMAX_MASK	GENMASK(31, 16)

/* ISC Clock Enable Register */
#define ISC_CLKEN               0x00000018

/* ISC Clock Disable Register */
#define ISC_CLKDIS              0x0000001c

/* ISC Clock Status Register */
#define ISC_CLKSR               0x00000020
#define ISC_CLKSR_SIP		BIT(31)

#define ISC_CLK(n)		BIT(n)

/* ISC Clock Configuration Register */
#define ISC_CLKCFG              0x00000024
#define ISC_CLKCFG_DIV_SHIFT(n) ((n) * 16)
#define ISC_CLKCFG_DIV_MASK(n)  GENMASK(((n) * 16 + 7), (n) * 16)
#define ISC_CLKCFG_SEL_SHIFT(n) ((n) * 16 + 8)
#define ISC_CLKCFG_SEL_MASK(n)  GENMASK(((n) * 17 + 8), ((n) * 16 + 8))

/* ISC Interrupt Enable Register */
#define ISC_INTEN       0x00000028

/* ISC Interrupt Disable Register */
#define ISC_INTDIS      0x0000002c

/* ISC Interrupt Mask Register */
#define ISC_INTMASK     0x00000030

/* ISC Interrupt Status Register */
#define ISC_INTSR       0x00000034

#define ISC_INT_DDONE		BIT(8)

Annotation

Implementation Notes