drivers/media/platform/nxp/imx8mq-mipi-csi2.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/nxp/imx8mq-mipi-csi2.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/nxp/imx8mq-mipi-csi2.c
Extension
.c
Size
28849 bytes
Lines
1093
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct imx8mq_plat_data {
	int (*enable)(struct csi_state *state, u32 hs_settle);
	void (*disable)(struct csi_state *state);
	bool use_reg_csr;
};

/*
 * The send level configures the number of entries that must accumulate in
 * the Pixel FIFO before the data will be transferred to the video output.
 * The exact value needed for this configuration is dependent on the rate at
 * which the sensor transfers data to the CSI-2 Controller and the user
 * video clock.
 *
 * The calculation is the classical rate-in rate-out type of problem: If the
 * video bandwidth is 10% faster than the incoming mipi data and the video
 * line length is 500 pixels, then the fifo should be allowed to fill
 * 10% of the line length or 50 pixels. If the gap data is ok, then the level
 * can be set to 16 and ignored.
 */
#define CSI2RX_SEND_LEVEL			64

struct csi_state {
	struct device *dev;
	const struct imx8mq_plat_data *pdata;
	void __iomem *regs;
	struct clk_bulk_data *clks;
	struct clk *esc_clk;
	u32 num_clks;
	struct reset_control *rst;
	struct regulator *mipi_phy_regulator;

	struct v4l2_subdev sd;
	struct media_pad pads[MIPI_CSI2_PADS_NUM];
	struct v4l2_async_notifier notifier;
	struct v4l2_subdev *src_sd;

	struct v4l2_mbus_config_mipi_csi2 bus;

	struct mutex lock; /* Protect state */
	u32 state;

	struct regmap *phy_gpr;
	u8 phy_gpr_reg;

	struct icc_path			*icc_path;
	s32				icc_path_bw;
};

/* -----------------------------------------------------------------------------
 * Format helpers
 */

struct csi2_pix_format {
	u32 code;
	u8 width;
};

/* -----------------------------------------------------------------------------
 * i.MX8MQ GPR
 */

#define	GPR_CSI2_1_RX_ENABLE		BIT(13)
#define	GPR_CSI2_1_VID_INTFC_ENB	BIT(12)
#define	GPR_CSI2_1_HSEL			BIT(10)
#define	GPR_CSI2_1_CONT_CLK_MODE	BIT(8)
#define	GPR_CSI2_1_S_PRG_RXHS_SETTLE(x)	(((x) & 0x3f) << 2)

static int imx8mq_gpr_enable(struct csi_state *state, u32 hs_settle)
{
	regmap_update_bits(state->phy_gpr,
			   state->phy_gpr_reg,
			   0x3fff,
			   GPR_CSI2_1_RX_ENABLE |
			   GPR_CSI2_1_VID_INTFC_ENB |
			   GPR_CSI2_1_HSEL |
			   GPR_CSI2_1_CONT_CLK_MODE |
			   GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));

	return 0;
}

static const struct imx8mq_plat_data imx8mq_data = {
	.enable = imx8mq_gpr_enable,
};

/* -----------------------------------------------------------------------------
 * i.MX8QXP
 */

#define CSI2SS_PL_CLK_INTERVAL_US		100

Annotation

Implementation Notes