drivers/media/platform/qcom/iris/iris_resources.c
Source file repositories/reference/linux-study-clean/drivers/media/platform/qcom/iris/iris_resources.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/qcom/iris/iris_resources.c- Extension
.c- Size
- 3006 bytes
- Lines
- 144
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/devfreq.hlinux/interconnect.hlinux/pm_domain.hlinux/pm_opp.hlinux/pm_runtime.hlinux/reset.hiris_core.hiris_resources.h
Detected Declarations
function Copyrightfunction iris_unset_icc_bwfunction iris_opp_set_ratefunction iris_enable_power_domainsfunction iris_disable_power_domainsfunction iris_prepare_enable_clockfunction iris_disable_unprepare_clock
Annotated Snippet
if (!strcmp(core->icc_tbl[i].name, "video-mem")) {
bw_kbps = icc_bw;
bw_prev = core->power.icc_bw;
bw_kbps = clamp_t(typeof(bw_kbps), bw_kbps,
icc_tbl[i].bw_min_kbps, icc_tbl[i].bw_max_kbps);
if (abs(bw_kbps - bw_prev) < BW_THRESHOLD && bw_prev)
return ret;
core->icc_tbl[i].avg_bw = bw_kbps;
core->power.icc_bw = bw_kbps;
break;
}
}
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
int iris_unset_icc_bw(struct iris_core *core)
{
u32 i;
core->power.icc_bw = 0;
for (i = 0; i < core->icc_count; i++) {
core->icc_tbl[i].avg_bw = 0;
core->icc_tbl[i].peak_bw = 0;
}
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
int iris_opp_set_rate(struct device *dev, unsigned long freq)
{
struct dev_pm_opp *opp __free(put_opp);
opp = devfreq_recommended_opp(dev, &freq, 0);
if (IS_ERR(opp))
return PTR_ERR(opp);
return dev_pm_opp_set_opp(dev, opp);
}
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
ret = pm_runtime_get_sync(pd_dev);
if (ret < 0)
return ret;
return ret;
}
int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;
pm_runtime_put_sync(pd_dev);
return 0;
}
static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type)
{
const struct platform_clk_data *clk_tbl;
u32 clk_cnt, i, j;
clk_tbl = core->iris_platform_data->clk_tbl;
clk_cnt = core->iris_platform_data->clk_tbl_size;
for (i = 0; i < clk_cnt; i++) {
if (clk_tbl[i].clk_type == clk_type) {
for (j = 0; core->clock_tbl && j < core->clk_count; j++) {
if (!strcmp(core->clock_tbl[j].id, clk_tbl[i].clk_name))
return core->clock_tbl[j].clk;
}
}
}
Annotation
- Immediate include surface: `linux/clk.h`, `linux/devfreq.h`, `linux/interconnect.h`, `linux/pm_domain.h`, `linux/pm_opp.h`, `linux/pm_runtime.h`, `linux/reset.h`, `iris_core.h`.
- Detected declarations: `function Copyright`, `function iris_unset_icc_bw`, `function iris_opp_set_rate`, `function iris_enable_power_domains`, `function iris_disable_power_domains`, `function iris_prepare_enable_clock`, `function iris_disable_unprepare_clock`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.