drivers/media/platform/qcom/iris/iris_vpu4x.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/qcom/iris/iris_vpu4x.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/qcom/iris/iris_vpu4x.c
Extension
.c
Size
11476 bytes
Lines
372
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/iopoll.h>
#include <linux/reset.h>

#include "iris_instance.h"
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"

#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST	(AON_MVP_NOC_RESET + 0x08)
#define CPU_CS_APV_BRIDGE_SYNC_RESET		(CPU_BASE_OFFS + 0x174)
#define MVP_NOC_RESET_REQ_MASK			0x70103
#define VPU_IDLE_BITS				0x7103
#define WRAPPER_EFUSE_MONITOR			(WRAPPER_BASE_OFFS + 0x08)

#define APV_CLK_HALT		BIT(1)
#define CORE_CLK_HALT		BIT(0)
#define CORE_PWR_ON		BIT(1)
#define DISABLE_VIDEO_APV_BIT	BIT(27)
#define DISABLE_VIDEO_VPP1_BIT	BIT(28)
#define DISABLE_VIDEO_VPP0_BIT	BIT(29)

static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 efuse_value)
{
	int ret;

	ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);
	if (ret)
		return ret;

	if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
		ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
					      [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode);
		if (ret)
			goto restore_hw_domain_mode;
	}

	if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
		ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
					      [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode);
		if (ret)
			goto restore_vpp0_domain_mode;
	}

	if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) {
		ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
					      [IRIS_APV_HW_POWER_DOMAIN], hw_mode);
		if (ret)
			goto restore_vpp1_domain_mode;
	}

	return 0;

restore_vpp1_domain_mode:
	if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
		dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN],
					!hw_mode);
restore_vpp0_domain_mode:
	if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
		dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
					!hw_mode);
restore_hw_domain_mode:
	dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);

	return ret;
}

static int iris_vpu4x_power_on_apv(struct iris_core *core)
{
	int ret;

	ret = iris_enable_power_domains(core,
					core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
	if (ret)
		return ret;

	ret = iris_prepare_enable_clock(core, IRIS_APV_HW_CLK);
	if (ret)
		goto disable_apv_hw_power_domain;

	return 0;

disable_apv_hw_power_domain:
	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);

	return ret;
}

Annotation

Implementation Notes