drivers/media/platform/qcom/venus/hfi_venus_io.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/qcom/venus/hfi_venus_io.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/qcom/venus/hfi_venus_io.h
Extension
.h
Size
5185 bytes
Lines
165
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __VENUS_HFI_VENUS_IO_H__
#define __VENUS_HFI_VENUS_IO_H__

#define VBIF_BASE				0x80000

#define VBIF_AXI_HALT_CTRL0			0x208
#define VBIF_AXI_HALT_CTRL1			0x20c

#define VBIF_AXI_HALT_CTRL0_HALT_REQ		BIT(0)
#define VBIF_AXI_HALT_CTRL1_HALT_ACK		BIT(0)
#define VBIF_AXI_HALT_ACK_TIMEOUT_US		500000

#define CPU_BASE				0xc0000

#define CPU_CS_BASE				(CPU_BASE + 0x12000)
#define CPU_IC_BASE				(CPU_BASE + 0x1f000)
#define CPU_BASE_V6				0xa0000
#define CPU_CS_BASE_V6				CPU_BASE_V6
#define CPU_IC_BASE_V6				(CPU_BASE_V6 + 0x138)

#define CPU_CS_A2HSOFTINTCLR			0x1c

#define VIDC_CTRL_INIT				0x48
#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK	0xfffffffe
#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT	1
#define VIDC_CTRL_INIT_CTRL_MASK		0x1
#define VIDC_CTRL_INIT_CTRL_SHIFT		0

/* HFI control status */
#define CPU_CS_SCIACMDARG0			0x4c
#define CPU_CS_SCIACMDARG0_MASK			0xff
#define CPU_CS_SCIACMDARG0_SHIFT		0x0
#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK	0xfe
#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT	0x1
#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK	0x1
#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT	0x0
#define CPU_CS_SCIACMDARG0_PC_READY		BIT(8)
#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK	BIT(30)

/* HFI queue table info */
#define CPU_CS_SCIACMDARG1			0x50

/* HFI queue table address */
#define CPU_CS_SCIACMDARG2			0x54

/* Venus cpu */
#define CPU_CS_SCIACMDARG3			0x58

#define CPU_CS_VCICMD				0x20
#define CPU_CS_VCICMD_ARP_OFF			BIT(0)

#define SFR_ADDR				0x5c
#define MMAP_ADDR				0x60
#define UC_REGION_ADDR				0x64
#define UC_REGION_SIZE				0x68

#define CPU_CS_H2XSOFTINTEN_V6			0x148

#define CPU_CS_X2RPMH_V6			0x168
#define CPU_CS_X2RPMH_MASK0_BMSK_V6		0x1
#define CPU_CS_X2RPMH_MASK0_SHFT_V6		0x0
#define CPU_CS_X2RPMH_MASK1_BMSK_V6		0x2
#define CPU_CS_X2RPMH_MASK1_SHFT_V6		0x1
#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6	0x4
#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6	0x3

/* Relative to CPU_IC_BASE */
#define CPU_IC_SOFTINT				0x18
#define CPU_IC_SOFTINT_V6			0x150
#define CPU_IC_SOFTINT_H2A_MASK			0x8000
#define CPU_IC_SOFTINT_H2A_SHIFT		0xf
#define CPU_IC_SOFTINT_H2A_SHIFT_V6		0x0

/* Venus wrapper */
#define WRAPPER_BASE_V6				0x000b0000
#define WRAPPER_BASE				0x000e0000

#define WRAPPER_HW_VERSION			0x00
#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK	0x78000000
#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT	28
#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK	0xfff0000
#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT	16
#define WRAPPER_HW_VERSION_STEP_VERSION_MASK	0xffff

#define WRAPPER_CLOCK_CONFIG			0x04

#define WRAPPER_INTR_STATUS			0x0c
#define WRAPPER_INTR_STATUS_A2HWD_MASK		0x10
#define WRAPPER_INTR_STATUS_A2HWD_SHIFT		0x4
#define WRAPPER_INTR_STATUS_A2H_MASK		0x4

Annotation

Implementation Notes