drivers/media/platform/renesas/rcar-csi2.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/renesas/rcar-csi2.c

File Facts

System: Linux kernel
Corpus path: drivers/media/platform/renesas/rcar-csi2.c
Extension: .c
Size: 79063 bytes
Lines: 2668
Domain: Driver Families
Bucket: drivers/media
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/delay.h
linux/interrupt.h
linux/io.h
linux/math64.h
linux/module.h
linux/of.h
linux/of_graph.h
linux/platform_device.h
linux/pm_runtime.h
linux/reset.h
linux/sys_soc.h
linux/units.h
media/mipi-csi2.h
media/v4l2-ctrls.h
media/v4l2-device.h
media/v4l2-fwnode.h
media/v4l2-mc.h
media/v4l2-subdev.h

Detected Declarations

struct rcar_csi2
struct rcsi2_cphy_setting
struct phtw_value
struct rcsi2_mbps_info
struct rcar_csi2_format
struct rcsi2_cphy_line_order
struct rcsi2_register_layout
struct rcar_csi2_info
struct rcar_csi2
struct rcsi2_d_phy_setting_v4h_lut_value
enum rcar_csi2_pads
function rcsi2_num_pads
function rcsi2_read
function rcsi2_write
function rcsi2_read16
function rcsi2_write16
function rcsi2_modify16
function rcsi2_phtw_write
function rcsi2_phtw_write_array
function rcsi2_mbps_to_info
function rcsi2_enter_standby_gen3
function rcsi2_enter_standby
function rcsi2_exit_standby
function rcsi2_wait_phy_start
function rcsi2_set_phypll
function rcsi2_get_active_lanes
function rcsi2_calc_mbps
function rcsi2_start_receiver_gen3
function rsci2_set_line_order
function rcsi2_wait_phy_start_v4h
function rcsi2_c_phy_setting_v4h
function rcsi2_d_phy_setting_v4h_lut_lookup
function rcsi2_d_phy_setting_v4h
function rcsi2_start_receiver_v4h
function rcsi2_d_phy_setting_v4m
function rcsi2_set_osc_freq
function rcsi2_init_common_v4m
function rcsi2_start_receiver_v4m
function rcsi2_start
function rcsi2_stop
function rcsi2_enable_streams
function rcsi2_disable_streams
function rcsi2_set_pad_format
function rcsi2_init_state
function rcsi2_irq
function rcsi2_irq_thread
function rcsi2_notify_bound
function rcsi2_notify_unbind

Annotated Snippet

struct rcsi2_cphy_setting {
	u16 msps;
	u16 rx2;
	u16 trio0;
	u16 trio1;
	u16 trio2;
	u16 lane27;
	u16 lane29;
};

static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = {
	{ .msps =   80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 },
	{ .msps =  100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 },
	{ .msps =  200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 },
	{ .msps =  300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 },
	{ .msps =  400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 },
	{ .msps =  500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 },
	{ .msps =  600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 },
	{ .msps =  700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 },
	{ .msps =  800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 },
	{ .msps =  900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 },
	{ .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 },
	{ .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 },
	{ .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 },
	{ .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 },
	{ .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
	{ .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
	{ .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 },
	{ .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
	{ .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
	{ .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
	{ .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 },
	{ .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
	{ .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
	{ .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
	{ .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
	{ .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 },
	{ .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
	{ /* sentinel */ },
};

/* V4M registers */
#define V4M_OVR1_REG					0x0848
#define V4M_OVR1_FORCERXMODE_3				BIT(12)
#define V4M_OVR1_FORCERXMODE_2				BIT(11)
#define V4M_OVR1_FORCERXMODE_1				BIT(10)
#define V4M_OVR1_FORCERXMODE_0				BIT(9)

#define V4M_FRXM_REG					0x2004
#define V4M_FRXM_FORCERXMODE_3				BIT(3)
#define V4M_FRXM_FORCERXMODE_2				BIT(2)
#define V4M_FRXM_FORCERXMODE_1				BIT(1)
#define V4M_FRXM_FORCERXMODE_0				BIT(0)

#define V4M_PHYPLL_REG					0x02050
#define V4M_CSI0CLKFCPR_REG				0x02054
#define V4M_PHTW_REG					0x02060
#define V4M_PHTR_REG					0x02064
#define V4M_PHTC_REG					0x02068

struct phtw_value {
	u8 data;
	u8 code;
};

struct rcsi2_mbps_info {
	u16 mbps;
	u8 reg;
	u16 osc_freq; /* V4M */
};

static const struct rcsi2_mbps_info phtw_mbps_v3u[] = {
	{ .mbps = 1500, .reg = 0xcc },
	{ .mbps = 1550, .reg = 0x1d },
	{ .mbps = 1600, .reg = 0x27 },
	{ .mbps = 1650, .reg = 0x30 },
	{ .mbps = 1700, .reg = 0x39 },
	{ .mbps = 1750, .reg = 0x42 },
	{ .mbps = 1800, .reg = 0x4b },
	{ .mbps = 1850, .reg = 0x55 },
	{ .mbps = 1900, .reg = 0x5e },

Annotation

Immediate include surface: `linux/delay.h`, `linux/interrupt.h`, `linux/io.h`, `linux/math64.h`, `linux/module.h`, `linux/of.h`, `linux/of_graph.h`, `linux/platform_device.h`.
Detected declarations: `struct rcar_csi2`, `struct rcsi2_cphy_setting`, `struct phtw_value`, `struct rcsi2_mbps_info`, `struct rcar_csi2_format`, `struct rcsi2_cphy_line_order`, `struct rcsi2_register_layout`, `struct rcar_csi2_info`, `struct rcar_csi2`, `struct rcsi2_d_phy_setting_v4h_lut_value`.
Atlas domain: Driver Families / drivers/media.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.