drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

File Facts

System: Linux kernel
Corpus path: drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
Extension: .h
Size: 77934 bytes
Lines: 1379
Domain: Driver Families
Bucket: drivers/media
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _RKISP1_REGS_H
#define _RKISP1_REGS_H

/* ISP_CTRL */
#define RKISP1_CIF_ISP_CTRL_ISP_ENABLE			BIT(0)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT		(0 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656		(1 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601		(2 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601	(3 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_DATA_MODE		(4 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656	(5 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656	(6 << 1)
#define RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE		BIT(4)
#define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA		BIT(6)
#define RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA			BIT(7)
#define RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT	BIT(8)
#define RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD			BIT(9)
#define RKISP1_CIF_ISP_CTRL_ISP_GEN_CFG_UPD		BIT(10)
#define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA		BIT(11)
#define RKISP1_CIF_ISP_CTRL_ISP_FLASH_MODE_ENA		BIT(12)
#define RKISP1_CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA		BIT(13)
#define RKISP1_CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA		BIT(14)

/* ISP_ACQ_PROP */
#define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE		BIT(0)
#define RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW		BIT(1)
#define RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW		BIT(2)
#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB		(0 << 3)
#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG		(1 << 3)
#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG		(2 << 3)
#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR		(3 << 3)
#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(pat)		((pat) << 3)
#define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR			(0 << 7)
#define RKISP1_CIF_ISP_ACQ_PROP_YCRYCB			(1 << 7)
#define RKISP1_CIF_ISP_ACQ_PROP_CBYCRY			(2 << 7)
#define RKISP1_CIF_ISP_ACQ_PROP_CRYCBY			(3 << 7)
#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL		(0 << 9)
#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN		(1 << 9)
#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ODD		(2 << 9)
#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B		(0 << 12)
#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO		(1 << 12)
#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB		(2 << 12)
#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO		(3 << 12)
#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB		(4 << 12)

/* VI_DPCL */
#define RKISP1_CIF_VI_DPCL_DMA_JPEG			(0 << 0)
#define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI		(1 << 0)
#define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG		(2 << 0)
#define RKISP1_CIF_VI_DPCL_CHAN_MODE_MP			(1 << 2)
#define RKISP1_CIF_VI_DPCL_CHAN_MODE_SP			(2 << 2)
#define RKISP1_CIF_VI_DPCL_CHAN_MODE_MPSP		(3 << 2)
#define RKISP1_CIF_VI_DPCL_DMA_SW_SPMUX			(0 << 4)
#define RKISP1_CIF_VI_DPCL_DMA_SW_SI			(1 << 4)
#define RKISP1_CIF_VI_DPCL_DMA_SW_IE			(2 << 4)
#define RKISP1_CIF_VI_DPCL_DMA_SW_JPEG			(3 << 4)
#define RKISP1_CIF_VI_DPCL_DMA_SW_ISP			(4 << 4)
#define RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL		(0 << 8)
#define RKISP1_CIF_VI_DPCL_IF_SEL_SMIA			(1 << 8)
#define RKISP1_CIF_VI_DPCL_IF_SEL_MIPI			(2 << 8)
#define RKISP1_CIF_VI_DPCL_DMA_IE_MUX_DMA		BIT(10)
#define RKISP1_CIF_VI_DPCL_DMA_SP_MUX_DMA		BIT(11)

/* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
#define RKISP1_CIF_ISP_OFF				BIT(0)
#define RKISP1_CIF_ISP_FRAME				BIT(1)
#define RKISP1_CIF_ISP_DATA_LOSS			BIT(2)
#define RKISP1_CIF_ISP_PIC_SIZE_ERROR			BIT(3)
#define RKISP1_CIF_ISP_AWB_DONE				BIT(4)
#define RKISP1_CIF_ISP_FRAME_IN				BIT(5)
#define RKISP1_CIF_ISP_V_START				BIT(6)
#define RKISP1_CIF_ISP_H_START				BIT(7)
#define RKISP1_CIF_ISP_FLASH_ON				BIT(8)
#define RKISP1_CIF_ISP_FLASH_OFF			BIT(9)
#define RKISP1_CIF_ISP_SHUTTER_ON			BIT(10)
#define RKISP1_CIF_ISP_SHUTTER_OFF			BIT(11)
#define RKISP1_CIF_ISP_AFM_SUM_OF			BIT(12)
#define RKISP1_CIF_ISP_AFM_LUM_OF			BIT(13)
#define RKISP1_CIF_ISP_AFM_FIN				BIT(14)
#define RKISP1_CIF_ISP_HIST_MEASURE_RDY			BIT(15)
#define RKISP1_CIF_ISP_FLASH_CAP			BIT(17)
#define RKISP1_CIF_ISP_EXP_END				BIT(18)
#define RKISP1_CIF_ISP_VSM_END				BIT(19)

/* ISP_ERR */
#define RKISP1_CIF_ISP_ERR_INFORM_SIZE			BIT(0)
#define RKISP1_CIF_ISP_ERR_IS_SIZE			BIT(1)
#define RKISP1_CIF_ISP_ERR_OUTFORM_SIZE			BIT(2)

/* MI_CTRL */

Annotation

Atlas domain: Driver Families / drivers/media.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.