drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
Source file repositories/reference/linux-study-clean/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c- Extension
.c- Size
- 24502 bytes
- Lines
- 595
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
media/v4l2-mem2mem.hrkvdec.hrkvdec-cabac.hrkvdec-rcb.hrkvdec-hevc-common.hrkvdec-vdpu383-regs.hrkvdec-bitwriter.h
Detected Declarations
struct rkvdec_hevc_sps_ppsstruct rkvdec_hevc_priv_tblstruct rkvdec_hevc_ctxfunction assemble_hw_ppsfunction rkvdec_write_regsfunction config_registersfunction rkvdec_hevc_validate_spsfunction rkvdec_hevc_startfunction rkvdec_hevc_stopfunction rkvdec_hevc_runfunction rkvdec_hevc_try_ctrl
Annotated Snippet
struct rkvdec_hevc_sps_pps {
u32 info[HEVC_SPS_SIZE / 8 / 4];
};
struct rkvdec_hevc_priv_tbl {
struct rkvdec_hevc_sps_pps param_set;
struct rkvdec_rps rps;
struct scaling_factor scaling_list;
u8 cabac_table[27456];
} __packed;
struct rkvdec_hevc_ctx {
struct rkvdec_aux_buf priv_tbl;
struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache;
struct vdpu383_regs_h26x regs;
};
static void assemble_hw_pps(struct rkvdec_ctx *ctx,
struct rkvdec_hevc_run *run)
{
struct rkvdec_hevc_ctx *h264_ctx = ctx->priv;
const struct v4l2_ctrl_hevc_sps *sps = run->sps;
const struct v4l2_ctrl_hevc_pps *pps = run->pps;
const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params;
struct rkvdec_hevc_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
struct rkvdec_hevc_sps_pps *hw_ps;
bool tiles_enabled;
s32 max_cu_width;
s32 pic_in_cts_width;
s32 pic_in_cts_height;
u16 log2_min_cb_size, width, height;
u16 column_width[22];
u16 row_height[22];
u8 pcm_enabled;
u32 i;
/*
* HW read the SPS/PPS information from PPS packet index by PPS id.
* offset from the base can be calculated by PPS_id * 32 (size per PPS
* packet unit). so the driver copy SPS/PPS information to the exact PPS
* packet unit for HW accessing.
*/
hw_ps = &priv_tbl->param_set;
memset(hw_ps, 0, sizeof(*hw_ps));
/* write sps */
rkvdec_set_bw_field(hw_ps->info, VIDEO_PARAMETER_SET_ID, sps->video_parameter_set_id);
rkvdec_set_bw_field(hw_ps->info, SEQ_PARAMETER_SET_ID, sps->seq_parameter_set_id);
rkvdec_set_bw_field(hw_ps->info, CHROMA_FORMAT_IDC, sps->chroma_format_idc);
log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
width = sps->pic_width_in_luma_samples;
height = sps->pic_height_in_luma_samples;
rkvdec_set_bw_field(hw_ps->info, PIC_WIDTH_IN_LUMA_SAMPLES, width);
rkvdec_set_bw_field(hw_ps->info, PIC_HEIGHT_IN_LUMA_SAMPLES, height);
rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_LUMA, sps->bit_depth_luma_minus8 + 8);
rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_CHROMA, sps->bit_depth_chroma_minus8 + 8);
rkvdec_set_bw_field(hw_ps->info, LOG2_MAX_PIC_ORDER_CNT_LSB,
sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE,
sps->log2_diff_max_min_luma_coding_block_size);
rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_LUMA_CODING_BLOCK_SIZE,
sps->log2_min_luma_coding_block_size_minus3 + 3);
rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_TRANSFORM_BLOCK_SIZE,
sps->log2_min_luma_transform_block_size_minus2 + 2);
rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE,
sps->log2_diff_max_min_luma_transform_block_size);
rkvdec_set_bw_field(hw_ps->info, MAX_TRANSFORM_HIERARCHY_DEPTH_INTER,
sps->max_transform_hierarchy_depth_inter);
rkvdec_set_bw_field(hw_ps->info, MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA,
sps->max_transform_hierarchy_depth_intra);
rkvdec_set_bw_field(hw_ps->info, SCALING_LIST_ENABLED_FLAG,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED));
rkvdec_set_bw_field(hw_ps->info, AMP_ENABLED_FLAG,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
rkvdec_set_bw_field(hw_ps->info, SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
rkvdec_set_bw_field(hw_ps->info, PCM_ENABLED_FLAG, pcm_enabled);
rkvdec_set_bw_field(hw_ps->info, PCM_SAMPLE_BIT_DEPTH_LUMA,
pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0);
rkvdec_set_bw_field(hw_ps->info, PCM_SAMPLE_BIT_DEPTH_CHROMA,
pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0);
rkvdec_set_bw_field(hw_ps->info, PCM_LOOP_FILTER_DISABLED_FLAG,
!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE,
sps->log2_diff_max_min_pcm_luma_coding_block_size);
Annotation
- Immediate include surface: `media/v4l2-mem2mem.h`, `rkvdec.h`, `rkvdec-cabac.h`, `rkvdec-rcb.h`, `rkvdec-hevc-common.h`, `rkvdec-vdpu383-regs.h`, `rkvdec-bitwriter.h`.
- Detected declarations: `struct rkvdec_hevc_sps_pps`, `struct rkvdec_hevc_priv_tbl`, `struct rkvdec_hevc_ctx`, `function assemble_hw_pps`, `function rkvdec_write_regs`, `function config_registers`, `function rkvdec_hevc_validate_sps`, `function rkvdec_hevc_start`, `function rkvdec_hevc_stop`, `function rkvdec_hevc_run`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.