drivers/media/platform/samsung/exynos4-is/fimc-is-regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/samsung/exynos4-is/fimc-is-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/samsung/exynos4-is/fimc-is-regs.h
Extension
.h
Size
5650 bytes
Lines
162
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef FIMC_IS_REG_H_
#define FIMC_IS_REG_H_

/* WDT_ISP register */
#define REG_WDT_ISP			0x00170000

/* MCUCTL registers base offset */
#define MCUCTL_BASE			0x00180000

/* MCU Controller Register */
#define MCUCTL_REG_MCUCTRL		(MCUCTL_BASE + 0x00)
#define MCUCTRL_MSWRST			(1 << 0)

/* Boot Base Offset Address Register */
#define MCUCTL_REG_BBOAR		(MCUCTL_BASE + 0x04)

/* Interrupt Generation Register 0 from Host CPU to VIC */
#define MCUCTL_REG_INTGR0		(MCUCTL_BASE + 0x08)
/* __n = 0...9 */
#define INTGR0_INTGC(__n)		(1 << ((__n) + 16))
/* __n = 0...5 */
#define INTGR0_INTGD(__n)		(1 << (__n))

/* Interrupt Clear Register 0 from Host CPU to VIC */
#define MCUCTL_REG_INTCR0		(MCUCTL_BASE + 0x0c)
/* __n = 0...9 */
#define INTCR0_INTGC(__n)		(1 << ((__n) + 16))
/* __n = 0...5 */
#define INTCR0_INTCD(__n)		(1 << ((__n) + 16))

/* Interrupt Mask Register 0 from Host CPU to VIC */
#define MCUCTL_REG_INTMR0		(MCUCTL_BASE + 0x10)
/* __n = 0...9 */
#define INTMR0_INTMC(__n)		(1 << ((__n) + 16))
/* __n = 0...5 */
#define INTMR0_INTMD(__n)		(1 << (__n))

/* Interrupt Status Register 0 from Host CPU to VIC */
#define MCUCTL_REG_INTSR0		(MCUCTL_BASE + 0x14)
/* __n (bit number) = 0...4 */
#define INTSR0_GET_INTSD(x, __n)	(((x) >> (__n)) & 0x1)
/* __n (bit number) = 0...9 */
#define INTSR0_GET_INTSC(x, __n)	(((x) >> ((__n) + 16)) & 0x1)

/* Interrupt Mask Status Register 0 from Host CPU to VIC */
#define MCUCTL_REG_INTMSR0		(MCUCTL_BASE + 0x18)
/* __n (bit number) = 0...4 */
#define INTMSR0_GET_INTMSD(x, __n)	(((x) >> (__n)) & 0x1)
/* __n (bit number) = 0...9 */
#define INTMSR0_GET_INTMSC(x, __n)	(((x) >> ((__n) + 16)) & 0x1)

/* Interrupt Generation Register 1 from ISP CPU to Host IC */
#define MCUCTL_REG_INTGR1		(MCUCTL_BASE + 0x1c)
/* __n = 0...9 */
#define INTGR1_INTGC(__n)		(1 << (__n))

/* Interrupt Clear Register 1 from ISP CPU to Host IC */
#define MCUCTL_REG_INTCR1		(MCUCTL_BASE + 0x20)
/* __n = 0...9 */
#define INTCR1_INTCC(__n)		(1 << (__n))

/* Interrupt Mask Register 1 from ISP CPU to Host IC */
#define MCUCTL_REG_INTMR1		(MCUCTL_BASE + 0x24)
/* __n = 0...9 */
#define INTMR1_INTMC(__n)		(1 << (__n))

/* Interrupt Status Register 1 from ISP CPU to Host IC */
#define MCUCTL_REG_INTSR1		(MCUCTL_BASE + 0x28)
/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
#define MCUCTL_REG_INTMSR1		(MCUCTL_BASE + 0x2c)

/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
#define MCUCTL_REG_INTCR2		(MCUCTL_BASE + 0x30)
/* __n = 0...5 */
#define INTCR2_INTCC(__n)		(1 << ((__n) + 16))

/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
#define MCUCTL_REG_INTMR2		(MCUCTL_BASE + 0x34)
/* __n = 0...25 */
#define INTMR2_INTMCIS(__n)		(1 << (__n))

/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
#define MCUCTL_REG_INTSR2		(MCUCTL_BASE + 0x38)
/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
#define MCUCTL_REG_INTMSR2		(MCUCTL_BASE + 0x3c)

/* General Purpose Output Control Register (0~17) */
#define MCUCTL_REG_GPOCTLR		(MCUCTL_BASE + 0x40)
/* __n = 0...17 */
#define GPOCTLR_GPOG(__n)		(1 << (__n))

Annotation

Implementation Notes