drivers/media/platform/samsung/exynos4-is/fimc-reg.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/samsung/exynos4-is/fimc-reg.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/samsung/exynos4-is/fimc-reg.h
Extension
.h
Size
13380 bytes
Lines
339
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef FIMC_REG_H_
#define FIMC_REG_H_

#include <linux/bitops.h>

#include "fimc-core.h"

/* Input source format */
#define FIMC_REG_CISRCFMT			0x00
#define FIMC_REG_CISRCFMT_ITU601_8BIT		BIT(31)
#define FIMC_REG_CISRCFMT_ITU601_16BIT		BIT(29)
#define FIMC_REG_CISRCFMT_ORDER422_YCBYCR	(0 << 14)
#define FIMC_REG_CISRCFMT_ORDER422_YCRYCB	(1 << 14)
#define FIMC_REG_CISRCFMT_ORDER422_CBYCRY	(2 << 14)
#define FIMC_REG_CISRCFMT_ORDER422_CRYCBY	(3 << 14)

/* Window offset */
#define FIMC_REG_CIWDOFST			0x04
#define FIMC_REG_CIWDOFST_OFF_EN		BIT(31)
#define FIMC_REG_CIWDOFST_CLROVFIY		BIT(30)
#define FIMC_REG_CIWDOFST_CLROVRLB		BIT(29)
#define FIMC_REG_CIWDOFST_HOROFF_MASK		(0x7ff << 16)
#define FIMC_REG_CIWDOFST_CLROVFICB		BIT(15)
#define FIMC_REG_CIWDOFST_CLROVFICR		BIT(14)
#define FIMC_REG_CIWDOFST_VEROFF_MASK		(0xfff << 0)

/* Global control */
#define FIMC_REG_CIGCTRL			0x08
#define FIMC_REG_CIGCTRL_SWRST			BIT(31)
#define FIMC_REG_CIGCTRL_CAMRST_A		BIT(30)
#define FIMC_REG_CIGCTRL_SELCAM_ITU_A		BIT(29)
#define FIMC_REG_CIGCTRL_TESTPAT_NORMAL		(0 << 27)
#define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR	(1 << 27)
#define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC	(2 << 27)
#define FIMC_REG_CIGCTRL_TESTPAT_VER_INC	(3 << 27)
#define FIMC_REG_CIGCTRL_TESTPAT_MASK		(3 << 27)
#define FIMC_REG_CIGCTRL_TESTPAT_SHIFT		27
#define FIMC_REG_CIGCTRL_INVPOLPCLK		BIT(26)
#define FIMC_REG_CIGCTRL_INVPOLVSYNC		BIT(25)
#define FIMC_REG_CIGCTRL_INVPOLHREF		BIT(24)
#define FIMC_REG_CIGCTRL_IRQ_OVFEN		BIT(22)
#define FIMC_REG_CIGCTRL_HREF_MASK		BIT(21)
#define FIMC_REG_CIGCTRL_IRQ_LEVEL		BIT(20)
#define FIMC_REG_CIGCTRL_IRQ_CLR		BIT(19)
#define FIMC_REG_CIGCTRL_IRQ_ENABLE		BIT(16)
#define FIMC_REG_CIGCTRL_SHDW_DISABLE		BIT(12)
/* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
#define FIMC_REG_CIGCTRL_SELWB_A		BIT(10)
#define FIMC_REG_CIGCTRL_CAM_JPEG		BIT(8)
#define FIMC_REG_CIGCTRL_SELCAM_MIPI_A		BIT(7)
#define FIMC_REG_CIGCTRL_CAMIF_SELWB		BIT(6)
/* 0 - ITU601; 1 - ITU709 */
#define FIMC_REG_CIGCTRL_CSC_ITU601_709		BIT(5)
#define FIMC_REG_CIGCTRL_INVPOLHSYNC		BIT(4)
#define FIMC_REG_CIGCTRL_SELCAM_MIPI		BIT(3)
#define FIMC_REG_CIGCTRL_INVPOLFIELD		BIT(1)
#define FIMC_REG_CIGCTRL_INTERLACE		BIT(0)

/* Window offset 2 */
#define FIMC_REG_CIWDOFST2			0x14
#define FIMC_REG_CIWDOFST2_HOROFF_MASK		(0xfff << 16)
#define FIMC_REG_CIWDOFST2_VEROFF_MASK		(0xfff << 0)

/* Output DMA Y/Cb/Cr plane start addresses */
#define FIMC_REG_CIOYSA(n)			(0x18 + (n) * 4)
#define FIMC_REG_CIOCBSA(n)			(0x28 + (n) * 4)
#define FIMC_REG_CIOCRSA(n)			(0x38 + (n) * 4)

/* Target image format */
#define FIMC_REG_CITRGFMT			0x48
#define FIMC_REG_CITRGFMT_INROT90		BIT(31)
#define FIMC_REG_CITRGFMT_YCBCR420		(0 << 29)
#define FIMC_REG_CITRGFMT_YCBCR422		(1 << 29)
#define FIMC_REG_CITRGFMT_YCBCR422_1P		(2 << 29)
#define FIMC_REG_CITRGFMT_RGB			(3 << 29)
#define FIMC_REG_CITRGFMT_FMT_MASK		(3 << 29)
#define FIMC_REG_CITRGFMT_HSIZE_MASK		(0xfff << 16)
#define FIMC_REG_CITRGFMT_FLIP_SHIFT		14
#define FIMC_REG_CITRGFMT_FLIP_NORMAL		(0 << 14)
#define FIMC_REG_CITRGFMT_FLIP_X_MIRROR		(1 << 14)
#define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR		(2 << 14)
#define FIMC_REG_CITRGFMT_FLIP_180		(3 << 14)
#define FIMC_REG_CITRGFMT_FLIP_MASK		(3 << 14)
#define FIMC_REG_CITRGFMT_OUTROT90		BIT(13)
#define FIMC_REG_CITRGFMT_VSIZE_MASK		(0xfff << 0)

/* Output DMA control */
#define FIMC_REG_CIOCTRL			0x4c
#define FIMC_REG_CIOCTRL_ORDER422_MASK		(3 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_YCBYCR	(0 << 0)

Annotation

Implementation Notes