drivers/media/platform/samsung/s3c-camif/camif-regs.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/samsung/s3c-camif/camif-regs.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/samsung/s3c-camif/camif-regs.c
Extension
.c
Size
17406 bytes
Lines
604
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (rem == 0) {
			*mburst = div;
			*rburst = div;
			break;
		}
		if (rem == div / 2 || rem == div / 4) {
			*mburst = div;
			*rburst = rem;
			break;
		}
	}
}

void camif_hw_set_output_dma(struct camif_vp *vp)
{
	struct camif_dev *camif = vp->camif;
	struct camif_frame *frame = &vp->out_frame;
	const struct camif_fmt *fmt = vp->out_fmt;
	unsigned int ymburst = 0, yrburst = 0;
	u32 cfg;

	camif_hw_set_out_dma_size(vp);

	if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV) {
		struct camif_dma_offset *offset = &frame->dma_offset;
		/* Set the input dma offsets. */
		cfg = S3C_CISS_OFFS_INITIAL(offset->initial);
		cfg |= S3C_CISS_OFFS_LINE(offset->line);
		camif_write(camif, S3C_CAMIF_REG_CISSY(vp->id), cfg);
		camif_write(camif, S3C_CAMIF_REG_CISSCB(vp->id), cfg);
		camif_write(camif, S3C_CAMIF_REG_CISSCR(vp->id), cfg);
	}

	/* Configure DMA burst values */
	camif_get_dma_burst(frame->rect.width, fmt->ybpp, &ymburst, &yrburst);

	cfg = camif_read(camif, S3C_CAMIF_REG_CICTRL(vp->id, vp->offset));
	cfg &= ~CICTRL_BURST_MASK;

	cfg |= CICTRL_YBURST1(ymburst) | CICTRL_YBURST2(yrburst);
	cfg |= CICTRL_CBURST1(ymburst / 2) | CICTRL_CBURST2(yrburst / 2);

	camif_write(camif, S3C_CAMIF_REG_CICTRL(vp->id, vp->offset), cfg);

	pr_debug("ymburst: %u, yrburst: %u\n", ymburst, yrburst);
}

void camif_hw_set_input_path(struct camif_vp *vp)
{
	u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_MSCTRL(vp->id));
	cfg &= ~MSCTRL_SEL_DMA_CAM;
	camif_write(vp->camif, S3C_CAMIF_REG_MSCTRL(vp->id), cfg);
}

void camif_hw_set_target_format(struct camif_vp *vp)
{
	struct camif_dev *camif = vp->camif;
	struct camif_frame *frame = &vp->out_frame;
	u32 cfg;

	pr_debug("fw: %d, fh: %d color: %d\n", frame->f_width,
		 frame->f_height, vp->out_fmt->color);

	cfg = camif_read(camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset));
	cfg &= ~CITRGFMT_TARGETSIZE_MASK;

	if (camif->variant->ip_revision == S3C244X_CAMIF_IP_REV) {
		/* We currently support only YCbCr 4:2:2 at the camera input */
		cfg |= CITRGFMT_IN422;
		cfg &= ~CITRGFMT_OUT422;
		if (vp->out_fmt->color == IMG_FMT_YCBCR422P)
			cfg |= CITRGFMT_OUT422;
	} else {
		cfg &= ~CITRGFMT_OUTFORMAT_MASK;
		switch (vp->out_fmt->color) {
		case IMG_FMT_RGB565...IMG_FMT_XRGB8888:
			cfg |= CITRGFMT_OUTFORMAT_RGB;
			break;
		case IMG_FMT_YCBCR420...IMG_FMT_YCRCB420:
			cfg |= CITRGFMT_OUTFORMAT_YCBCR420;
			break;
		case IMG_FMT_YCBCR422P:
			cfg |= CITRGFMT_OUTFORMAT_YCBCR422;
			break;
		case IMG_FMT_YCBYCR422...IMG_FMT_CRYCBY422:
			cfg |= CITRGFMT_OUTFORMAT_YCBCR422I;
			break;
		}
	}

Annotation

Implementation Notes