drivers/media/platform/samsung/s5p-mfc/regs-mfc.h
Source file repositories/reference/linux-study-clean/drivers/media/platform/samsung/s5p-mfc/regs-mfc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/samsung/s5p-mfc/regs-mfc.h- Extension
.h- Size
- 18706 bytes
- Lines
- 460
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
linux/kernel.hlinux/sizes.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _REGS_FIMV_H
#define _REGS_FIMV_H
#include <linux/kernel.h>
#include <linux/sizes.h>
#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
/* Number of bits that the buffer address should be shifted for particular
* MFC buffers. */
#define S5P_FIMV_START_ADDR 0x0000
#define S5P_FIMV_END_ADDR 0xe008
#define S5P_FIMV_SW_RESET 0x0000
#define S5P_FIMV_RISC_HOST_INT 0x0008
/* Command from HOST to RISC */
#define S5P_FIMV_HOST2RISC_CMD 0x0030
#define S5P_FIMV_HOST2RISC_ARG1 0x0034
#define S5P_FIMV_HOST2RISC_ARG2 0x0038
#define S5P_FIMV_HOST2RISC_ARG3 0x003c
#define S5P_FIMV_HOST2RISC_ARG4 0x0040
/* Command from RISC to HOST */
#define S5P_FIMV_RISC2HOST_CMD 0x0044
#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF
#define S5P_FIMV_RISC2HOST_ARG1 0x0048
#define S5P_FIMV_RISC2HOST_ARG2 0x004c
#define S5P_FIMV_RISC2HOST_ARG3 0x0050
#define S5P_FIMV_RISC2HOST_ARG4 0x0054
#define S5P_FIMV_FW_VERSION 0x0058
#define S5P_FIMV_SYS_MEM_SZ 0x005c
#define S5P_FIMV_FW_STATUS 0x0080
/* Memory controller register */
#define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508
#define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c
#define S5P_FIMV_MC_STATUS 0x0510
/* Common register */
#define S5P_FIMV_COMMON_BASE_A 0x0600
#define S5P_FIMV_COMMON_BASE_B 0x0700
/* Decoder */
#define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A)
#define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B)
/* H.264 decoding */
#define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
/* vertical neighbor motion vector */
#define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
/* neighbor pixels for intra pred */
#define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)
/* H264 motion vector */
/* MPEG4 decoding */
#define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
/* neighbor AC/DC coeff. */
#define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
/* upper neighbor motion vector */
#define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
/* subseq. anchor motion vector */
#define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
/* overlap transform line */
#define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)
/* syntax parser */
/* H.263 decoding */
#define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
#define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
#define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
#define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
/* VC-1 decoding */
#define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
#define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
#define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
#define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
#define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)
/* bitplane3 */
#define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)
/* bitplane2 */
#define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)
/* bitplane1 */
/* Encoder */
#define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)
#define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/sizes.h`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.