drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
Extension
.c
Size
81769 bytes
Lines
2829
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hdmirx_buffer {
	struct vb2_v4l2_buffer vb;
	struct list_head queue;
	u32 buff_addr[VIDEO_MAX_PLANES];
};

struct hdmirx_stream {
	struct snps_hdmirx_dev *hdmirx_dev;
	struct video_device vdev;
	struct vb2_queue buf_queue;
	struct list_head buf_head;
	struct hdmirx_buffer *curr_buf;
	struct hdmirx_buffer *next_buf;
	struct v4l2_pix_format_mplane pixm;
	const struct v4l2_format_info *out_finfo;
	struct mutex vlock; /* to lock resources associated with video buffer and video device */
	spinlock_t vbq_lock; /* to lock video buffer queue */
	bool stopping;
	wait_queue_head_t wq_stopped;
	u32 sequence;
	u32 line_flag_int_cnt;
	u32 irq_stat;
};

struct snps_hdmirx_dev {
	struct device *dev;
	struct hdmirx_stream stream;
	struct v4l2_device v4l2_dev;
	struct v4l2_ctrl_handler hdl;
	struct v4l2_ctrl *detect_tx_5v_ctrl;
	struct v4l2_ctrl *rgb_range;
	struct v4l2_ctrl *content_type;
	struct v4l2_dv_timings timings;
	struct gpio_desc *detect_5v_gpio;
	struct delayed_work delayed_work_hotplug;
	struct delayed_work delayed_work_res_change;
	struct hdmirx_cec *cec;
	struct mutex phy_rw_lock; /* to protect phy r/w configuration */
	struct mutex stream_lock; /* to lock video stream capture */
	struct mutex work_lock; /* to lock the critical section of hotplug event */
	struct reset_control_bulk_data resets[HDMIRX_NUM_RST];
	struct clk_bulk_data *clks;
	struct regmap *grf;
	struct regmap *vo1_grf;
	struct completion cr_read_done;
	struct completion cr_write_done;
	struct completion timer_base_lock;
	struct completion avi_pkt_rcv;
	struct dentry *debugfs_dir;
	struct v4l2_debugfs_if *infoframes;
	enum hdmirx_pix_fmt pix_fmt;
	void __iomem *regs;
	int hdmi_irq;
	int dma_irq;
	int det_irq;
	bool hpd_trigger_level_high;
	bool tmds_clk_ratio;
	bool plugged;
	int num_clks;
	u32 edid_blocks_written;
	u32 cur_fmt_fourcc;
	u32 color_depth;
	spinlock_t rst_lock; /* to lock register access */
	u8 edid[EDID_NUM_BLOCKS_MAX * EDID_BLOCK_SIZE];
};

static const struct v4l2_dv_timings cea640x480 = V4L2_DV_BT_CEA_640X480P59_94;

static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
	.type = V4L2_DV_BT_656_1120,
	.reserved = { 0 },
	V4L2_INIT_BT_TIMINGS(640, 4096,			/* min/max width */
			     480, 2160,			/* min/max height */
			     20000000, 600000000,	/* min/max pixelclock */
			     /* standards */
			     V4L2_DV_BT_STD_CEA861,
			     /* capabilities */
			     V4L2_DV_BT_CAP_PROGRESSIVE |
			     V4L2_DV_BT_CAP_INTERLACED)
};

static void hdmirx_writel(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val)
{
	guard(spinlock_irqsave)(&hdmirx_dev->rst_lock);

	writel(val, hdmirx_dev->regs + reg);
}

static u32 hdmirx_readl(struct snps_hdmirx_dev *hdmirx_dev, int reg)
{

Annotation

Implementation Notes