drivers/media/platform/ti/cal/cal_regs.h
Source file repositories/reference/linux-study-clean/drivers/media/platform/ti/cal/cal_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/ti/cal/cal_regs.h- Extension
.h- Size
- 19472 bytes
- Lines
- 464
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __TI_CAL_REGS_H
#define __TI_CAL_REGS_H
/*
* struct cal_dev.flags possibilities
*
* DRA72_CAL_PRE_ES2_LDO_DISABLE:
* Errata i913: CSI2 LDO Needs to be disabled when module is powered on
*
* Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
* LDOs on the device are disabled if CSI-2 module is powered on
* (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
* | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
* current draw on the module supply in active mode.
*
* Errata does not apply when CSI-2 module is powered off
* (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
*
* SW Workaround:
* Set the following register bits to disable the LDO,
* which is essentially CSI2 REG10 bit 6:
*
* Core 0: 0x4845 B828 = 0x0000 0040
* Core 1: 0x4845 B928 = 0x0000 0040
*/
#define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
/* CAL register offsets */
#define CAL_HL_REVISION 0x0000
#define CAL_HL_HWINFO 0x0004
#define CAL_HL_SYSCONFIG 0x0010
#define CAL_HL_IRQ_EOI 0x001c
#define CAL_HL_IRQSTATUS_RAW(m) (0x20U + (m) * 0x10U)
#define CAL_HL_IRQSTATUS(m) (0x24U + (m) * 0x10U)
#define CAL_HL_IRQENABLE_SET(m) (0x28U + (m) * 0x10U)
#define CAL_HL_IRQENABLE_CLR(m) (0x2cU + (m) * 0x10U)
#define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U)
#define CAL_CTRL 0x100
#define CAL_CTRL1 0x104
#define CAL_LINE_NUMBER_EVT 0x108
#define CAL_VPORT_CTRL1 0x120
#define CAL_VPORT_CTRL2 0x124
#define CAL_BYS_CTRL1 0x130
#define CAL_BYS_CTRL2 0x134
#define CAL_RD_DMA_CTRL 0x140
#define CAL_RD_DMA_PIX_ADDR 0x144
#define CAL_RD_DMA_PIX_OFST 0x148
#define CAL_RD_DMA_XSIZE 0x14c
#define CAL_RD_DMA_YSIZE 0x150
#define CAL_RD_DMA_INIT_ADDR 0x154
#define CAL_RD_DMA_INIT_OFST 0x168
#define CAL_RD_DMA_CTRL2 0x16c
#define CAL_WR_DMA_CTRL(m) (0x200U + (m) * 0x10U)
#define CAL_WR_DMA_ADDR(m) (0x204U + (m) * 0x10U)
#define CAL_WR_DMA_OFST(m) (0x208U + (m) * 0x10U)
#define CAL_WR_DMA_XSIZE(m) (0x20cU + (m) * 0x10U)
#define CAL_CSI2_PPI_CTRL(m) (0x300U + (m) * 0x80U)
#define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + (m) * 0x80U)
#define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + (m) * 0x80U)
#define CAL_CSI2_SHORT_PACKET(m) (0x30cU + (m) * 0x80U)
#define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + (m) * 0x80U)
#define CAL_CSI2_TIMING(m) (0x314U + (m) * 0x80U)
#define CAL_CSI2_VC_IRQENABLE(m) (0x318U + (m) * 0x80U)
#define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + (m) * 0x80U)
#define CAL_CSI2_CTX(phy, csi2_ctx) (0x330U + (phy) * 0x80U + (csi2_ctx) * 4)
#define CAL_CSI2_STATUS(phy, csi2_ctx) (0x350U + (phy) * 0x80U + (csi2_ctx) * 4)
/* CAL CSI2 PHY register offsets */
#define CAL_CSI2_PHY_REG0 0x000
#define CAL_CSI2_PHY_REG1 0x004
#define CAL_CSI2_PHY_REG2 0x008
#define CAL_CSI2_PHY_REG10 0x028
/* CAL Control Module Core Camerrx Control register offsets */
#define CM_CTRL_CORE_CAMERRX_CONTROL 0x000
/*********************************************************************
* Field Definition Macros
*********************************************************************/
#define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
#define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
#define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
#define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
#define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
#define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
#define CAL_HL_REVISION_SCHEME_H08 1
#define CAL_HL_REVISION_SCHEME_LEGACY 0
Annotation
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.