drivers/media/platform/ti/omap3isp/isp.c
Source file repositories/reference/linux-study-clean/drivers/media/platform/ti/omap3isp/isp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/ti/omap3isp/isp.c- Extension
.c- Size
- 64261 bytes
- Lines
- 2456
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/clkdev.hlinux/delay.hlinux/device.hlinux/dma-mapping.hlinux/i2c.hlinux/interrupt.hlinux/mfd/syscon.hlinux/module.hlinux/omap-iommu.hlinux/platform_device.hlinux/property.hlinux/regulator/consumer.hlinux/slab.hlinux/sched.hlinux/vmalloc.hasm/dma-iommu.hmedia/v4l2-common.hmedia/v4l2-fwnode.hmedia/v4l2-device.hmedia/v4l2-mc.hisp.hispreg.hispccdc.hisppreview.hispresizer.hispcsi2.hispccp2.hisph3a.hisphist.h
Detected Declarations
enum isp_of_phyfunction omap3isp_flushfunction isp_xclk_updatefunction isp_xclk_preparefunction isp_xclk_unpreparefunction isp_xclk_enablefunction isp_xclk_disablefunction isp_xclk_recalc_ratefunction isp_xclk_calc_dividerfunction isp_xclk_determine_ratefunction isp_xclk_set_ratefunction isp_xclk_initfunction isp_xclk_cleanupfunction isp_enable_interruptsfunction isp_disable_interruptsfunction isp_core_initfunction omap3isp_configure_bridgefunction omap3isp_hist_dma_donefunction isp_isr_dbgfunction isp_isr_sblfunction isp_isrfunction isp_pipeline_enablefunction isp_pipeline_wait_resizerfunction isp_pipeline_wait_previewfunction isp_pipeline_wait_ccdcfunction isp_pipeline_waitfunction isp_pipeline_disablefunction omap3isp_pipeline_set_streamfunction omap3isp_pipeline_cancel_streamfunction isp_pipeline_resumefunction isp_pipeline_suspendfunction isp_pipeline_is_lastfunction isp_suspend_module_pipelinefunction isp_resume_module_pipelinefunction isp_suspend_modulesfunction isp_resume_modulesfunction isp_resetfunction isp_save_contextfunction isp_restore_contextfunction isp_save_ctxfunction isp_restore_ctxfunction omap3isp_sbl_enablefunction omap3isp_sbl_disablefunction omap3isp_module_sync_idlefunction omap3isp_module_sync_is_stoppingfunction __isp_subclk_updatefunction omap3isp_subclk_enablefunction omap3isp_subclk_disable
Annotated Snippet
omap3isp_stat_pcr_busy(&isp->isp_hist)) {
/* Histogram cannot be enabled in this frame anymore */
atomic_set(&isp->isp_hist.buf_err, 1);
dev_dbg(isp->dev,
"hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
}
}
static inline void __maybe_unused isp_isr_dbg(struct isp_device *isp,
u32 irqstatus)
{
static const char *name[] = {
"CSIA_IRQ",
"res1",
"res2",
"CSIB_LCM_IRQ",
"CSIB_IRQ",
"res5",
"res6",
"res7",
"CCDC_VD0_IRQ",
"CCDC_VD1_IRQ",
"CCDC_VD2_IRQ",
"CCDC_ERR_IRQ",
"H3A_AF_DONE_IRQ",
"H3A_AWB_DONE_IRQ",
"res14",
"res15",
"HIST_DONE_IRQ",
"CCDC_LSC_DONE",
"CCDC_LSC_PREFETCH_COMPLETED",
"CCDC_LSC_PREFETCH_ERROR",
"PRV_DONE_IRQ",
"CBUFF_IRQ",
"res22",
"res23",
"RSZ_DONE_IRQ",
"OVF_IRQ",
"res26",
"res27",
"MMU_ERR_IRQ",
"OCP_ERR_IRQ",
"SEC_ERR_IRQ",
"HS_VS_IRQ",
};
int i;
dev_dbg(isp->dev, "ISP IRQ: ");
for (i = 0; i < ARRAY_SIZE(name); i++) {
if ((1 << i) & irqstatus)
printk(KERN_CONT "%s ", name[i]);
}
printk(KERN_CONT "\n");
}
static void isp_isr_sbl(struct isp_device *isp)
{
struct device *dev = isp->dev;
struct isp_pipeline *pipe;
u32 sbl_pcr;
/*
* Handle shared buffer logic overflows for video buffers.
* ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
*/
sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
if (sbl_pcr)
dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
if (pipe != NULL)
pipe->error = true;
}
if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
if (pipe != NULL)
pipe->error = true;
}
if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
if (pipe != NULL)
pipe->error = true;
}
Annotation
- Immediate include surface: `linux/clk.h`, `linux/clkdev.h`, `linux/delay.h`, `linux/device.h`, `linux/dma-mapping.h`, `linux/i2c.h`, `linux/interrupt.h`, `linux/mfd/syscon.h`.
- Detected declarations: `enum isp_of_phy`, `function omap3isp_flush`, `function isp_xclk_update`, `function isp_xclk_prepare`, `function isp_xclk_unprepare`, `function isp_xclk_enable`, `function isp_xclk_disable`, `function isp_xclk_recalc_rate`, `function isp_xclk_calc_divider`, `function isp_xclk_determine_rate`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.