drivers/media/platform/ti/omap3isp/ispreg.h
Source file repositories/reference/linux-study-clean/drivers/media/platform/ti/omap3isp/ispreg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/ti/omap3isp/ispreg.h- Extension
.h- Size
- 54910 bytes
- Lines
- 1519
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef OMAP3_ISP_REG_H
#define OMAP3_ISP_REG_H
#define CM_CAM_MCLK_HZ 172800000 /* Hz */
/* ISP module register offset */
#define ISP_REVISION (0x000)
#define ISP_SYSCONFIG (0x004)
#define ISP_SYSSTATUS (0x008)
#define ISP_IRQ0ENABLE (0x00C)
#define ISP_IRQ0STATUS (0x010)
#define ISP_IRQ1ENABLE (0x014)
#define ISP_IRQ1STATUS (0x018)
#define ISP_TCTRL_GRESET_LENGTH (0x030)
#define ISP_TCTRL_PSTRB_REPLAY (0x034)
#define ISP_CTRL (0x040)
#define ISP_SECURE (0x044)
#define ISP_TCTRL_CTRL (0x050)
#define ISP_TCTRL_FRAME (0x054)
#define ISP_TCTRL_PSTRB_DELAY (0x058)
#define ISP_TCTRL_STRB_DELAY (0x05C)
#define ISP_TCTRL_SHUT_DELAY (0x060)
#define ISP_TCTRL_PSTRB_LENGTH (0x064)
#define ISP_TCTRL_STRB_LENGTH (0x068)
#define ISP_TCTRL_SHUT_LENGTH (0x06C)
#define ISP_PING_PONG_ADDR (0x070)
#define ISP_PING_PONG_MEM_RANGE (0x074)
#define ISP_PING_PONG_BUF_SIZE (0x078)
/* CCP2 receiver registers */
#define ISPCCP2_REVISION (0x000)
#define ISPCCP2_SYSCONFIG (0x004)
#define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
#define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
(0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO \
(0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
(0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
#define ISPCCP2_SYSSTATUS (0x008)
#define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
#define ISPCCP2_LC01_IRQENABLE (0x00C)
#define ISPCCP2_LC01_IRQSTATUS (0x010)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2)
#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1)
#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
#define ISPCCP2_LC23_IRQENABLE (0x014)
#define ISPCCP2_LC23_IRQSTATUS (0x018)
#define ISPCCP2_LCM_IRQENABLE (0x02C)
#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1)
#define ISPCCP2_LCM_IRQSTATUS (0x030)
#define ISPCCP2_CTRL (0x040)
#define ISPCCP2_CTRL_IF_EN BIT(0)
#define ISPCCP2_CTRL_PHY_SEL BIT(1)
#define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
#define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
#define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
#define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
#define ISPCCP2_CTRL_IO_OUT_SEL BIT(2)
#define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
#define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
#define ISPCCP2_CTRL_MODE BIT(4)
#define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9)
#define ISPCCP2_CTRL_INV BIT(10)
#define ISPCCP2_CTRL_INV_MASK 0x1
#define ISPCCP2_CTRL_INV_SHIFT 10
#define ISPCCP2_CTRL_VP_ONLY_EN BIT(11)
#define ISPCCP2_CTRL_VP_CLK_POL BIT(12)
#define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
#define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
#define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
#define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
#define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */
#define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
#define ISPCCP2_DBG (0x044)
#define ISPCCP2_GNQ (0x048)
Annotation
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.