drivers/media/platform/verisilicon/hantro_g1_regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/verisilicon/hantro_g1_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/verisilicon/hantro_g1_regs.h
Extension
.h
Size
19556 bytes
Lines
357
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef HANTRO_G1_REGS_H_
#define HANTRO_G1_REGS_H_

#define G1_SWREG(nr)                 ((nr) * 4)

/* Decoder registers. */
#define G1_REG_INTERRUPT				0x004
#define     G1_REG_INTERRUPT_DEC_PIC_INF		BIT(24)
#define     G1_REG_INTERRUPT_DEC_TIMEOUT		BIT(18)
#define     G1_REG_INTERRUPT_DEC_SLICE_INT		BIT(17)
#define     G1_REG_INTERRUPT_DEC_ERROR_INT		BIT(16)
#define     G1_REG_INTERRUPT_DEC_ASO_INT		BIT(15)
#define     G1_REG_INTERRUPT_DEC_BUFFER_INT		BIT(14)
#define     G1_REG_INTERRUPT_DEC_BUS_INT		BIT(13)
#define     G1_REG_INTERRUPT_DEC_RDY_INT		BIT(12)
#define     G1_REG_INTERRUPT_DEC_IRQ			BIT(8)
#define     G1_REG_INTERRUPT_DEC_IRQ_DIS		BIT(4)
#define     G1_REG_INTERRUPT_DEC_E			BIT(0)
#define G1_REG_CONFIG					0x008
#define     G1_REG_CONFIG_DEC_AXI_RD_ID(x)		(((x) & 0xff) << 24)
#define     G1_REG_CONFIG_DEC_TIMEOUT_E			BIT(23)
#define     G1_REG_CONFIG_DEC_STRSWAP32_E		BIT(22)
#define     G1_REG_CONFIG_DEC_STRENDIAN_E		BIT(21)
#define     G1_REG_CONFIG_DEC_INSWAP32_E		BIT(20)
#define     G1_REG_CONFIG_DEC_OUTSWAP32_E		BIT(19)
#define     G1_REG_CONFIG_DEC_DATA_DISC_E		BIT(18)
#define     G1_REG_CONFIG_TILED_MODE_MSB		BIT(17)
#define     G1_REG_CONFIG_DEC_OUT_TILED_E		BIT(17)
#define     G1_REG_CONFIG_DEC_LATENCY(x)		(((x) & 0x3f) << 11)
#define     G1_REG_CONFIG_DEC_CLK_GATE_E		BIT(10)
#define     G1_REG_CONFIG_DEC_IN_ENDIAN			BIT(9)
#define     G1_REG_CONFIG_DEC_OUT_ENDIAN		BIT(8)
#define     G1_REG_CONFIG_PRIORITY_MODE(x)		(((x) & 0x7) << 5)
#define     G1_REG_CONFIG_TILED_MODE_LSB		BIT(7)
#define     G1_REG_CONFIG_DEC_ADV_PRE_DIS		BIT(6)
#define     G1_REG_CONFIG_DEC_SCMD_DIS			BIT(5)
#define     G1_REG_CONFIG_DEC_MAX_BURST(x)		(((x) & 0x1f) << 0)
#define G1_REG_DEC_CTRL0				0x00c
#define     G1_REG_DEC_CTRL0_DEC_MODE(x)		(((x) & 0xf) << 28)
#define     G1_REG_DEC_CTRL0_RLC_MODE_E			BIT(27)
#define     G1_REG_DEC_CTRL0_SKIP_MODE			BIT(26)
#define     G1_REG_DEC_CTRL0_DIVX3_E			BIT(25)
#define     G1_REG_DEC_CTRL0_PJPEG_E			BIT(24)
#define     G1_REG_DEC_CTRL0_PIC_INTERLACE_E		BIT(23)
#define     G1_REG_DEC_CTRL0_PIC_FIELDMODE_E		BIT(22)
#define     G1_REG_DEC_CTRL0_PIC_B_E			BIT(21)
#define     G1_REG_DEC_CTRL0_PIC_INTER_E		BIT(20)
#define     G1_REG_DEC_CTRL0_PIC_TOPFIELD_E		BIT(19)
#define     G1_REG_DEC_CTRL0_FWD_INTERLACE_E		BIT(18)
#define     G1_REG_DEC_CTRL0_SORENSON_E			BIT(17)
#define     G1_REG_DEC_CTRL0_REF_TOPFIELD_E		BIT(16)
#define     G1_REG_DEC_CTRL0_DEC_OUT_DIS		BIT(15)
#define     G1_REG_DEC_CTRL0_FILTERING_DIS		BIT(14)
#define     G1_REG_DEC_CTRL0_WEBP_E			BIT(13)
#define     G1_REG_DEC_CTRL0_MVC_E			BIT(13)
#define     G1_REG_DEC_CTRL0_PIC_FIXED_QUANT		BIT(13)
#define     G1_REG_DEC_CTRL0_WRITE_MVS_E		BIT(12)
#define     G1_REG_DEC_CTRL0_REFTOPFIRST_E		BIT(11)
#define     G1_REG_DEC_CTRL0_SEQ_MBAFF_E		BIT(10)
#define     G1_REG_DEC_CTRL0_PICORD_COUNT_E		BIT(9)
#define     G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E		BIT(8)
#define     G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x)		(((x) & 0xff) << 0)
/* Setting AXI ID to 0xff to get auto generated ID to avoid possible conflicts */
#define     G1_REG_DEC_CTRL0_DEC_AXI_AUTO		G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0xff)
#define G1_REG_DEC_CTRL1				0x010
#define     G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x)		(((x) & 0x1ff) << 23)
#define     G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x)		(((x) & 0xf) << 19)
#define     G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x)		(((x) & 0xff) << 11)
#define     G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x)		(((x) & 0xf) << 7)
#define     G1_REG_DEC_CTRL1_ALT_SCAN_E			BIT(6)
#define     G1_REG_DEC_CTRL1_TOPFIELDFIRST_E		BIT(5)
#define     G1_REG_DEC_CTRL1_REF_FRAMES(x)		(((x) & 0x1f) << 0)
#define     G1_REG_DEC_CTRL1_PIC_MB_W_EXT(x)		(((x) & 0x7) << 3)
#define     G1_REG_DEC_CTRL1_PIC_MB_H_EXT(x)		(((x) & 0x7) << 0)
#define     G1_REG_DEC_CTRL1_PIC_REFER_FLAG		BIT(0)
#define G1_REG_DEC_CTRL2				0x014
#define     G1_REG_DEC_CTRL2_STRM_START_BIT(x)		(((x) & 0x3f) << 26)
#define     G1_REG_DEC_CTRL2_SYNC_MARKER_E		BIT(25)
#define     G1_REG_DEC_CTRL2_TYPE1_QUANT_E		BIT(24)
#define     G1_REG_DEC_CTRL2_CH_QP_OFFSET(x)		(((x) & 0x1f) << 19)
#define     G1_REG_DEC_CTRL2_CH_QP_OFFSET2(x)		(((x) & 0x1f) << 14)
#define     G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E		BIT(0)
#define     G1_REG_DEC_CTRL2_INTRADC_VLC_THR(x)		(((x) & 0x7) << 16)
#define     G1_REG_DEC_CTRL2_VOP_TIME_INCR(x)		(((x) & 0xffff) << 0)
#define     G1_REG_DEC_CTRL2_DQ_PROFILE			BIT(24)
#define     G1_REG_DEC_CTRL2_DQBI_LEVEL			BIT(23)
#define     G1_REG_DEC_CTRL2_RANGE_RED_FRM_E		BIT(22)
#define     G1_REG_DEC_CTRL2_FAST_UVMC_E		BIT(20)
#define     G1_REG_DEC_CTRL2_TRANSDCTAB			BIT(17)
#define     G1_REG_DEC_CTRL2_TRANSACFRM(x)		(((x) & 0x3) << 15)

Annotation

Implementation Notes