drivers/media/platform/verisilicon/rockchip_vpu2_regs.h

Source file repositories/reference/linux-study-clean/drivers/media/platform/verisilicon/rockchip_vpu2_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/verisilicon/rockchip_vpu2_regs.h
Extension
.h
Size
33696 bytes
Lines
601
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ROCKCHIP_VPU2_REGS_H_
#define ROCKCHIP_VPU2_REGS_H_

/* Encoder registers. */
#define VEPU_REG_VP8_QUT_1ST(i)			(0x000 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_DC_Y2(x)			(((x) & 0x3fff) << 16)
#define     VEPU_REG_VP8_QUT_DC_Y1(x)			(((x) & 0x3fff) << 0)
#define VEPU_REG_VP8_QUT_2ND(i)			(0x004 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_AC_Y1(x)			(((x) & 0x3fff) << 16)
#define     VEPU_REG_VP8_QUT_DC_CHR(x)			(((x) & 0x3fff) << 0)
#define VEPU_REG_VP8_QUT_3RD(i)			(0x008 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_AC_CHR(x)			(((x) & 0x3fff) << 16)
#define     VEPU_REG_VP8_QUT_AC_Y2(x)			(((x) & 0x3fff) << 0)
#define VEPU_REG_VP8_QUT_4TH(i)			(0x00c + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_ZB_DC_CHR(x)		(((x) & 0x1ff) << 18)
#define     VEPU_REG_VP8_QUT_ZB_DC_Y2(x)		(((x) & 0x1ff) << 9)
#define     VEPU_REG_VP8_QUT_ZB_DC_Y1(x)		(((x) & 0x1ff) << 0)
#define VEPU_REG_VP8_QUT_5TH(i)			(0x010 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_ZB_AC_CHR(x)		(((x) & 0x1ff) << 18)
#define     VEPU_REG_VP8_QUT_ZB_AC_Y2(x)		(((x) & 0x1ff) << 9)
#define     VEPU_REG_VP8_QUT_ZB_AC_Y1(x)		(((x) & 0x1ff) << 0)
#define VEPU_REG_VP8_QUT_6TH(i)			(0x014 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_RND_DC_CHR(x)		(((x) & 0xff) << 16)
#define     VEPU_REG_VP8_QUT_RND_DC_Y2(x)		(((x) & 0xff) << 8)
#define     VEPU_REG_VP8_QUT_RND_DC_Y1(x)		(((x) & 0xff) << 0)
#define VEPU_REG_VP8_QUT_7TH(i)			(0x018 + ((i) * 0x24))
#define     VEPU_REG_VP8_QUT_RND_AC_CHR(x)		(((x) & 0xff) << 16)
#define     VEPU_REG_VP8_QUT_RND_AC_Y2(x)		(((x) & 0xff) << 8)
#define     VEPU_REG_VP8_QUT_RND_AC_Y1(x)		(((x) & 0xff) << 0)
#define VEPU_REG_VP8_QUT_8TH(i)			(0x01c + ((i) * 0x24))
#define     VEPU_REG_VP8_SEG_FILTER_LEVEL(x)		(((x) & 0x3f) << 25)
#define     VEPU_REG_VP8_DEQUT_DC_CHR(x)		(((x) & 0xff) << 17)
#define     VEPU_REG_VP8_DEQUT_DC_Y2(x)			(((x) & 0x1ff) << 8)
#define     VEPU_REG_VP8_DEQUT_DC_Y1(x)			(((x) & 0xff) << 0)
#define VEPU_REG_VP8_QUT_9TH(i)			(0x020 + ((i) * 0x24))
#define     VEPU_REG_VP8_DEQUT_AC_CHR(x)		(((x) & 0x1ff) << 18)
#define     VEPU_REG_VP8_DEQUT_AC_Y2(x)			(((x) & 0x1ff) << 9)
#define     VEPU_REG_VP8_DEQUT_AC_Y1(x)			(((x) & 0x1ff) << 0)
#define VEPU_REG_ADDR_VP8_SEG_MAP		0x06c
#define VEPU_REG_VP8_INTRA_4X4_PENALTY(i)	(0x070 + ((i) * 0x4))
#define     VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x)		(((x) & 0xfff) << 0)
#define     VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x)		(((x) & 0xfff) << 16)
#define VEPU_REG_VP8_INTRA_16X16_PENALTY(i)	(0x084 + ((i) * 0x4))
#define     VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x)	(((x) & 0xfff) << 0)
#define     VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x)	(((x) & 0xfff) << 16)
#define VEPU_REG_VP8_CONTROL			0x0a0
#define     VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x)		(((x) & 0x1f) << 24)
#define     VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x)	(((x) & 0x7f) << 16)
#define     VEPU_REG_VP8_INTER_TYPE_BIT_COST(x)		(((x) & 0xfff) << 0)
#define VEPU_REG_VP8_REF_FRAME_VAL		0x0a4
#define     VEPU_REG_VP8_COEF_DMV_PENALTY(x)		(((x) & 0xfff) << 16)
#define     VEPU_REG_VP8_REF_FRAME(x)			(((x) & 0xfff) << 0)
#define VEPU_REG_VP8_LOOP_FILTER_REF_DELTA	0x0a8
#define     VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x)	(((x) & 0x7f) << 16)
#define     VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x)	(((x) & 0x7f) << 8)
#define     VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x)		(((x) & 0x7f) << 0)
#define VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA	0x0ac
#define     VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x)	(((x) & 0x7f) << 16)
#define     VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x)	(((x) & 0x7f) << 8)
#define     VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x)		(((x) & 0x7f) << 0)
#define	VEPU_REG_JPEG_LUMA_QUAT(i)		(0x000 + ((i) * 0x4))
#define	VEPU_REG_JPEG_CHROMA_QUAT(i)		(0x040 + ((i) * 0x4))
#define VEPU_REG_INTRA_SLICE_BITMAP(i)		(0x0b0 + ((i) * 0x4))
#define VEPU_REG_ADDR_VP8_DCT_PART(i)		(0x0b0 + ((i) * 0x4))
#define VEPU_REG_INTRA_AREA_CTRL		0x0b8
#define     VEPU_REG_INTRA_AREA_TOP(x)			(((x) & 0xff) << 24)
#define     VEPU_REG_INTRA_AREA_BOTTOM(x)		(((x) & 0xff) << 16)
#define     VEPU_REG_INTRA_AREA_LEFT(x)			(((x) & 0xff) << 8)
#define     VEPU_REG_INTRA_AREA_RIGHT(x)		(((x) & 0xff) << 0)
#define VEPU_REG_CIR_INTRA_CTRL			0x0bc
#define     VEPU_REG_CIR_INTRA_FIRST_MB(x)		(((x) & 0xffff) << 16)
#define     VEPU_REG_CIR_INTRA_INTERVAL(x)		(((x) & 0xffff) << 0)
#define VEPU_REG_ADDR_IN_PLANE_0		0x0c0
#define VEPU_REG_ADDR_IN_PLANE_1		0x0c4
#define VEPU_REG_ADDR_IN_PLANE_2		0x0c8
#define VEPU_REG_STR_HDR_REM_MSB		0x0cc
#define VEPU_REG_STR_HDR_REM_LSB		0x0d0
#define VEPU_REG_STR_BUF_LIMIT			0x0d4
#define VEPU_REG_AXI_CTRL			0x0d8
#define     VEPU_REG_AXI_CTRL_READ_ID(x)		(((x) & 0xff) << 24)
#define     VEPU_REG_AXI_CTRL_WRITE_ID(x)		(((x) & 0xff) << 16)
#define     VEPU_REG_AXI_CTRL_BURST_LEN(x)		(((x) & 0x3f) << 8)
#define     VEPU_REG_AXI_CTRL_INCREMENT_MODE(x)		(((x) & 0x01) << 2)
#define     VEPU_REG_AXI_CTRL_BIRST_DISCARD(x)		(((x) & 0x01) << 1)
#define     VEPU_REG_AXI_CTRL_BIRST_DISABLE		BIT(0)
#define VEPU_QP_ADJUST_MAD_DELTA_ROI		0x0dc
#define     VEPU_REG_ROI_QP_DELTA_1			(((x) & 0xf) << 12)
#define     VEPU_REG_ROI_QP_DELTA_2			(((x) & 0xf) << 8)
#define     VEPU_REG_MAD_QP_ADJUSTMENT			(((x) & 0xf) << 0)
#define VEPU_REG_ADDR_REF_LUMA			0x0e0

Annotation

Implementation Notes