drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
Source file repositories/reference/linux-study-clean/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c- Extension
.c- Size
- 82377 bytes
- Lines
- 2269
- Domain
- Driver Families
- Bucket
- drivers/media
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
media/v4l2-mem2mem.hhantro.hhantro_v4l2.hrockchip_vpu981_regs.h
Detected Declarations
struct rockchip_av1_film_grainenum rockchip_av1_tx_modefunction rockchip_vpu981_get_frame_indexfunction rockchip_vpu981_get_order_hintfunction rockchip_vpu981_av1_dec_frame_reffunction rockchip_vpu981_av1_dec_frame_unreffunction rockchip_vpu981_av1_dec_clean_refsfunction rockchip_vpu981_av1_dec_luma_sizefunction rockchip_vpu981_av1_dec_chroma_sizefunction rockchip_vpu981_av1_dec_tiles_freefunction rockchip_vpu981_av1_dec_tiles_reallocatefunction rockchip_vpu981_av1_dec_exitfunction rockchip_vpu981_av1_dec_initfunction rockchip_vpu981_av1_dec_prepare_runfunction rockchip_vpu981_av1_dec_get_msbfunction rockchip_vpu981_av1_dec_resolve_divisor_32function rockchip_vpu981_av1_dec_get_shear_paramsfunction rockchip_vpu981_av1_dec_set_global_modelfunction rockchip_vpu981_av1_tile_log2function rockchip_vpu981_av1_dec_set_tile_infofunction rockchip_vpu981_av1_dec_get_distfunction rockchip_vpu981_av1_dec_set_frame_sign_biasfunction rockchip_vpu981_av1_dec_set_reffunction rockchip_vpu981_av1_dec_set_sign_biasfunction rockchip_vpu981_av1_dec_set_segmentationfunction rockchip_vpu981_av1_dec_is_losslessfunction rockchip_vpu981_av1_dec_set_loopfilterfunction rockchip_vpu981_av1_dec_update_probfunction rockchip_vpu981_av1_dec_donefunction rockchip_vpu981_av1_dec_set_probfunction rockchip_vpu981_av1_dec_init_scaling_functionfunction rockchip_vpu981_av1_dec_set_fgsfunction rockchip_vpu981_av1_dec_set_cdeffunction rockchip_vpu981_av1_dec_set_lrfunction rockchip_vpu981_av1_dec_set_superres_paramsfunction rockchip_vpu981_av1_dec_set_picture_dimensionsfunction rockchip_vpu981_av1_dec_set_other_framesfunction rockchip_vpu981_av1_dec_set_reference_framesfunction rockchip_vpu981_av1_get_hardware_tx_modefunction rockchip_vpu981_av1_dec_set_parametersfunction rockchip_vpu981_av1_dec_set_input_bufferfunction rockchip_vpu981_av1_dec_set_output_bufferfunction rockchip_vpu981_av1_dec_runfunction rockchip_vpu981_postproc_enablefunction rockchip_vpu981_postproc_disable
Annotated Snippet
struct rockchip_av1_film_grain {
u8 scaling_lut_y[256];
u8 scaling_lut_cb[256];
u8 scaling_lut_cr[256];
s16 cropped_luma_grain_block[4096];
s16 cropped_chroma_grain_block[1024 * 2];
};
static const short div_lut[DIV_LUT_NUM + 1] = {
16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768,
15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142,
15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564,
14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028,
13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530,
13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066,
13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633,
12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228,
12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848,
11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491,
11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155,
11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838,
10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538,
10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255,
10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986,
9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732,
9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489,
9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259,
9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039,
9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830,
8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630,
8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439,
8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257,
8240, 8224, 8208, 8192,
};
static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref)
{
struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
u64 timestamp;
int i, idx = frame->ref_frame_idx[ref];
if (idx >= V4L2_AV1_TOTAL_REFS_PER_FRAME || idx < 0)
return AV1_INVALID_IDX;
timestamp = frame->reference_frame_ts[idx];
for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) {
if (!av1_dec->frame_refs[i].used)
continue;
if (av1_dec->frame_refs[i].timestamp == timestamp)
return i;
}
return AV1_INVALID_IDX;
}
static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref)
{
struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
int idx = rockchip_vpu981_get_frame_index(ctx, ref);
if (idx != AV1_INVALID_IDX)
return av1_dec->frame_refs[idx].order_hint;
return 0;
}
static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx,
u64 timestamp)
{
struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
int i;
for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) {
int j;
if (av1_dec->frame_refs[i].used)
continue;
av1_dec->frame_refs[i].width = frame->frame_width_minus_1 + 1;
av1_dec->frame_refs[i].height = frame->frame_height_minus_1 + 1;
av1_dec->frame_refs[i].mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8);
av1_dec->frame_refs[i].mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8);
av1_dec->frame_refs[i].timestamp = timestamp;
av1_dec->frame_refs[i].frame_type = frame->frame_type;
av1_dec->frame_refs[i].order_hint = frame->order_hint;
av1_dec->frame_refs[i].vb2_ref = hantro_get_dst_buf(ctx);
Annotation
- Immediate include surface: `media/v4l2-mem2mem.h`, `hantro.h`, `hantro_v4l2.h`, `rockchip_vpu981_regs.h`.
- Detected declarations: `struct rockchip_av1_film_grain`, `enum rockchip_av1_tx_mode`, `function rockchip_vpu981_get_frame_index`, `function rockchip_vpu981_get_order_hint`, `function rockchip_vpu981_av1_dec_frame_ref`, `function rockchip_vpu981_av1_dec_frame_unref`, `function rockchip_vpu981_av1_dec_clean_refs`, `function rockchip_vpu981_av1_dec_luma_size`, `function rockchip_vpu981_av1_dec_chroma_size`, `function rockchip_vpu981_av1_dec_tiles_free`.
- Atlas domain: Driver Families / drivers/media.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.