drivers/media/platform/verisilicon/sunxi_vpu_hw.c

Source file repositories/reference/linux-study-clean/drivers/media/platform/verisilicon/sunxi_vpu_hw.c

File Facts

System
Linux kernel
Corpus path
drivers/media/platform/verisilicon/sunxi_vpu_hw.c
Extension
.c
Size
2974 bytes
Lines
130
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Allwinner Hantro G2 VPU codec driver
 *
 * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
 */

#include <linux/clk.h>

#include "hantro.h"

static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = {
	{
		.fourcc = V4L2_PIX_FMT_NV12,
		.codec_mode = HANTRO_MODE_NONE,
		.postprocessed = true,
		.frmsize = {
			.min_width = FMT_MIN_WIDTH,
			.max_width = FMT_UHD_WIDTH,
			.step_width = 32,
			.min_height = FMT_MIN_HEIGHT,
			.max_height = FMT_UHD_HEIGHT,
			.step_height = 32,
		},
	},
	{
		.fourcc = V4L2_PIX_FMT_P010,
		.codec_mode = HANTRO_MODE_NONE,
		.postprocessed = true,
		.frmsize = {
			.min_width = FMT_MIN_WIDTH,
			.max_width = FMT_UHD_WIDTH,
			.step_width = 32,
			.min_height = FMT_MIN_HEIGHT,
			.max_height = FMT_UHD_HEIGHT,
			.step_height = 32,
		},
	},
};

static const struct hantro_fmt sunxi_vpu_dec_fmts[] = {
	{
		.fourcc = V4L2_PIX_FMT_NV12_4L4,
		.codec_mode = HANTRO_MODE_NONE,
		.match_depth = true,
		.frmsize = {
			.min_width = FMT_MIN_WIDTH,
			.max_width = FMT_UHD_WIDTH,
			.step_width = 32,
			.min_height = FMT_MIN_HEIGHT,
			.max_height = FMT_UHD_HEIGHT,
			.step_height = 32,
		},
	},
	{
		.fourcc = V4L2_PIX_FMT_P010_4L4,
		.codec_mode = HANTRO_MODE_NONE,
		.match_depth = true,
		.frmsize = {
			.min_width = FMT_MIN_WIDTH,
			.max_width = FMT_UHD_WIDTH,
			.step_width = 32,
			.min_height = FMT_MIN_HEIGHT,
			.max_height = FMT_UHD_HEIGHT,
			.step_height = 32,
		},
	},
	{
		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
		.codec_mode = HANTRO_MODE_VP9_DEC,
		.max_depth = 2,
		.frmsize = {
			.min_width = FMT_MIN_WIDTH,
			.max_width = FMT_UHD_WIDTH,
			.step_width = 32,
			.min_height = FMT_MIN_HEIGHT,
			.max_height = FMT_UHD_HEIGHT,
			.step_height = 32,
		},
	},
};

static int sunxi_vpu_hw_init(struct hantro_dev *vpu)
{
	clk_set_rate(vpu->clocks[0].clk, 300000000);

	return 0;
}

static void sunxi_vpu_reset(struct hantro_ctx *ctx)

Annotation

Implementation Notes