drivers/media/rc/fintek-cir.h

Source file repositories/reference/linux-study-clean/drivers/media/rc/fintek-cir.h

File Facts

System
Linux kernel
Corpus path
drivers/media/rc/fintek-cir.h
Extension
.h
Size
5985 bytes
Lines
232
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct fintek_dev {
	struct pnp_dev *pdev;
	struct rc_dev *rdev;

	spinlock_t fintek_lock;

	/* for rx */
	u8 buf[RX_BUF_LEN];
	unsigned int pkts;

	struct {
		spinlock_t lock;
		u8 buf[TX_BUF_LEN];
		unsigned int buf_count;
		unsigned int cur_buf_num;
		wait_queue_head_t queue;
	} tx;

	/* Config register index/data port pair */
	u32 cr_ip;
	u32 cr_dp;

	/* hardware I/O settings */
	unsigned long cir_addr;
	int cir_irq;
	int cir_port_len;

	/* hardware id */
	u8 chip_major;
	u8 chip_minor;
	u16 chip_vendor;
	u8 logical_dev_cir;

	/* hardware features */
	bool hw_learning_capable;
	bool hw_tx_capable;

	/* rx settings */
	bool learning_enabled;
	bool carrier_detect_enabled;

	enum {
		CMD_HEADER = 0,
		SUBCMD,
		CMD_DATA,
		PARSE_IRDATA,
	} parser_state;

	u8 cmd, rem;

	/* carrier period = 1 / frequency */
	u32 carrier;
};

/* buffer packet constants, largely identical to mceusb.c */
#define BUF_PULSE_BIT		0x80
#define BUF_LEN_MASK		0x1f
#define BUF_SAMPLE_MASK		0x7f

#define BUF_COMMAND_HEADER	0x9f
#define BUF_COMMAND_MASK	0xe0
#define BUF_COMMAND_NULL	0x00
#define BUF_HW_CMD_HEADER	0xff
#define BUF_CMD_G_REVISION	0x0b
#define BUF_CMD_S_CARRIER	0x06
#define BUF_CMD_S_TIMEOUT	0x0c
#define BUF_CMD_SIG_END		0x01
#define BUF_CMD_S_TXMASK	0x08
#define BUF_CMD_S_RXSENSOR	0x14
#define BUF_RSP_PULSE_COUNT	0x15

#define CIR_SAMPLE_PERIOD	50

/*
 * Configuration Register:
 *  Index Port
 *  Data Port
 */
#define CR_INDEX_PORT		0x2e
#define CR_DATA_PORT		0x2f

/* Possible alternate values, depends on how the chip is wired */
#define CR_INDEX_PORT2		0x4e
#define CR_DATA_PORT2		0x4f

/*
 * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
 * active. 1 = 0x4e, 0 = 0x2e
 */
#define PORT_SEL_PORT_4E_EN	0x10

Annotation

Implementation Notes