drivers/media/usb/cx231xx/cx231xx-conf-reg.h

Source file repositories/reference/linux-study-clean/drivers/media/usb/cx231xx/cx231xx-conf-reg.h

File Facts

System
Linux kernel
Corpus path
drivers/media/usb/cx231xx/cx231xx-conf-reg.h
Extension
.h
Size
24813 bytes
Lines
484
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
			video capture devices

   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>

 */

#ifndef _POLARIS_REG_H_
#define _POLARIS_REG_H_

#define BOARD_CFG_STAT          0x0
#define TS_MODE_REG             0x4
#define TS1_CFG_REG             0x8
#define TS1_LENGTH_REG          0xc
#define TS2_CFG_REG             0x10
#define TS2_LENGTH_REG          0x14
#define EP_MODE_SET             0x18
#define CIR_PWR_PTN1            0x1c
#define CIR_PWR_PTN2            0x20
#define CIR_PWR_PTN3            0x24
#define CIR_PWR_MASK0           0x28
#define CIR_PWR_MASK1           0x2c
#define CIR_PWR_MASK2           0x30
#define CIR_GAIN                0x34
#define CIR_CAR_REG             0x38
#define CIR_OT_CFG1             0x40
#define CIR_OT_CFG2             0x44
#define GBULK_BIT_EN            0x68
#define PWR_CTL_EN              0x74

/* Polaris Endpoints capture mask for register EP_MODE_SET */
#define ENABLE_EP1              0x01   /* Bit[0]=1 */
#define ENABLE_EP2              0x02   /* Bit[1]=1 */
#define ENABLE_EP3              0x04   /* Bit[2]=1 */
#define ENABLE_EP4              0x08   /* Bit[3]=1 */
#define ENABLE_EP5              0x10   /* Bit[4]=1 */
#define ENABLE_EP6              0x20   /* Bit[5]=1 */

/* Bit definition for register PWR_CTL_EN */
#define PWR_MODE_MASK           0x17f
#define PWR_AV_EN               0x08   /* bit3 */
#define PWR_ISO_EN              0x40   /* bit6 */
#define PWR_AV_MODE             0x30   /* bit4,5  */
#define PWR_TUNER_EN            0x04   /* bit2 */
#define PWR_DEMOD_EN            0x02   /* bit1 */
#define I2C_DEMOD_EN            0x01   /* bit0 */
#define PWR_RESETOUT_EN         0x100  /* bit8 */

enum AV_MODE{
	POLARIS_AVMODE_DEFAULT = 0,
	POLARIS_AVMODE_DIGITAL = 0x10,
	POLARIS_AVMODE_ANALOGT_TV = 0x20,
	POLARIS_AVMODE_ENXTERNAL_AV = 0x30,

};

/* Colibri Registers */

#define SINGLE_ENDED            0x0
#define LOW_IF                  0x4
#define EU_IF                   0x9
#define US_IF                   0xa

#define SUP_BLK_TUNE1           0x00
#define SUP_BLK_TUNE2           0x01
#define SUP_BLK_TUNE3           0x02
#define SUP_BLK_XTAL            0x03
#define SUP_BLK_PLL1            0x04
#define SUP_BLK_PLL2            0x05
#define SUP_BLK_PLL3            0x06
#define SUP_BLK_REF             0x07
#define SUP_BLK_PWRDN           0x08
#define SUP_BLK_TESTPAD         0x09
#define ADC_COM_INT5_STAB_REF   0x0a
#define ADC_COM_QUANT           0x0b
#define ADC_COM_BIAS1           0x0c
#define ADC_COM_BIAS2           0x0d
#define ADC_COM_BIAS3           0x0e
#define TESTBUS_CTRL            0x12

#define FLD_PWRDN_TUNING_BIAS	0x10
#define FLD_PWRDN_ENABLE_PLL	0x08
#define FLD_PWRDN_PD_BANDGAP	0x04
#define FLD_PWRDN_PD_BIAS	0x02
#define FLD_PWRDN_PD_TUNECK	0x01


#define ADC_STATUS_CH1          0x20
#define ADC_STATUS_CH2          0x40
#define ADC_STATUS_CH3          0x60

Annotation

Implementation Notes