drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h

Source file repositories/reference/linux-study-clean/drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h

File Facts

System
Linux kernel
Corpus path
drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h
Extension
.h
Size
5818 bytes
Lines
194
Domain
Driver Families
Bucket
drivers/media
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef STV06XX_HDCS_H_
#define STV06XX_HDCS_H_

#include "stv06xx_sensor.h"

#define HDCS_REG_CONFIG(sd)	(IS_1020(sd) ? HDCS20_CONFIG : HDCS00_CONFIG)
#define HDCS_REG_CONTROL(sd)	(IS_1020(sd) ? HDCS20_CONTROL : HDCS00_CONTROL)

#define HDCS_1X00_DEF_WIDTH	360
#define HDCS_1X00_DEF_HEIGHT	296

#define HDCS_1020_DEF_WIDTH	352
#define HDCS_1020_DEF_HEIGHT	292

#define HDCS_1020_BOTTOM_Y_SKIP	4

#define HDCS_CLK_FREQ_MHZ	25

#define HDCS_ADC_START_SIG_DUR	3

/* LSB bit of I2C or register address signifies write (0) or read (1) */
/* I2C Registers common for both HDCS-1000/1100 and HDCS-1020 */
/* Identifications Register */
#define HDCS_IDENT		(0x00 << 1)
/* Status Register */
#define HDCS_STATUS		(0x01 << 1)
/* Interrupt Mask Register */
#define HDCS_IMASK		(0x02 << 1)
/* Pad Control Register */
#define HDCS_PCTRL		(0x03 << 1)
/* Pad Drive Control Register */
#define HDCS_PDRV		(0x04 << 1)
/* Interface Control Register */
#define HDCS_ICTRL		(0x05 << 1)
/* Interface Timing Register */
#define HDCS_ITMG		(0x06 << 1)
/* Baud Fraction Register */
#define HDCS_BFRAC		(0x07 << 1)
/* Baud Rate Register */
#define HDCS_BRATE		(0x08 << 1)
/* ADC Control Register */
#define HDCS_ADCCTRL		(0x09 << 1)
/* First Window Row Register */
#define HDCS_FWROW		(0x0a << 1)
/* First Window Column Register */
#define HDCS_FWCOL		(0x0b << 1)
/* Last Window Row Register */
#define HDCS_LWROW		(0x0c << 1)
/* Last Window Column Register */
#define HDCS_LWCOL		(0x0d << 1)
/* Timing Control Register */
#define HDCS_TCTRL		(0x0e << 1)
/* PGA Gain Register: Even Row, Even Column */
#define HDCS_ERECPGA		(0x0f << 1)
/* PGA Gain Register: Even Row, Odd Column */
#define HDCS_EROCPGA		(0x10 << 1)
/* PGA Gain Register: Odd Row, Even Column */
#define HDCS_ORECPGA		(0x11 << 1)
/* PGA Gain Register: Odd Row, Odd Column */
#define HDCS_OROCPGA		(0x12 << 1)
/* Row Exposure Low Register */
#define HDCS_ROWEXPL		(0x13 << 1)
/* Row Exposure High Register */
#define HDCS_ROWEXPH		(0x14 << 1)

/* I2C Registers only for HDCS-1000/1100 */
/* Sub-Row Exposure Low Register */
#define HDCS00_SROWEXPL		(0x15 << 1)
/* Sub-Row Exposure High Register */
#define HDCS00_SROWEXPH		(0x16 << 1)
/* Configuration Register */
#define HDCS00_CONFIG		(0x17 << 1)
/* Control Register */
#define HDCS00_CONTROL		(0x18 << 1)

/* I2C Registers only for HDCS-1020 */
/* Sub-Row Exposure Register */
#define HDCS20_SROWEXP		(0x15 << 1)
/* Error Control Register */
#define HDCS20_ERROR		(0x16 << 1)
/* Interface Timing 2 Register */
#define HDCS20_ITMG2		(0x17 << 1)
/* Interface Control 2 Register	*/
#define HDCS20_ICTRL2		(0x18 << 1)
/* Horizontal Blank Register */
#define HDCS20_HBLANK		(0x19 << 1)
/* Vertical Blank Register */
#define HDCS20_VBLANK		(0x1a << 1)
/* Configuration Register */
#define HDCS20_CONFIG		(0x1b << 1)

Annotation

Implementation Notes