drivers/memory/emif.c
Source file repositories/reference/linux-study-clean/drivers/memory/emif.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/memory/emif.c- Extension
.c- Size
- 34974 bytes
- Lines
- 1177
- Domain
- Driver Families
- Bucket
- drivers/memory
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cleanup.hlinux/err.hlinux/kernel.hlinux/reboot.hlinux/platform_data/emif_plat.hlinux/io.hlinux/device.hlinux/platform_device.hlinux/interrupt.hlinux/slab.hlinux/of.hlinux/debugfs.hlinux/seq_file.hlinux/module.hlinux/list.hlinux/spinlock.hlinux/pm.hemif.hjedec_ddr.hof_memory.h
Detected Declarations
struct emif_datafunction do_emif_regdump_showfunction emif_regdump_showfunction emif_mr4_showfunction emif_debugfs_initfunction emif_debugfs_exitfunction get_emif_bus_widthfunction set_lpmodefunction do_freq_updatefunction list_for_each_entryfunction get_zq_config_regfunction get_temp_alert_configfunction get_pwr_mgmt_ctrlfunction get_temperature_levelfunction setup_temperature_sensitive_regsfunction handle_temp_alertfunction emif_interrupt_handlerfunction emif_threaded_isrfunction clear_all_interruptsfunction disable_and_clear_all_interruptsfunction setup_interruptsfunction emif_onetime_settingsfunction get_default_timingsfunction is_dev_data_validfunction is_custom_config_validfunction of_get_custom_configsfunction of_get_ddr_infofunction EMIF1function emif_probefunction emif_removefunction emif_shutdown
Annotated Snippet
struct emif_data {
u8 duplicate;
u8 temperature_level;
u8 lpmode;
struct list_head node;
void __iomem *base;
struct device *dev;
struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
struct emif_regs *curr_regs;
struct emif_platform_data *plat_data;
struct dentry *debugfs_root;
struct device_node *np_ddr;
};
static struct emif_data *emif1;
static DEFINE_SPINLOCK(emif_lock);
static LIST_HEAD(device_list);
static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
struct emif_regs *regs)
{
u32 type = emif->plat_data->device_info->type;
u32 ip_rev = emif->plat_data->ip_rev;
seq_printf(s, "EMIF register cache dump for %dMHz\n",
regs->freq/1000000);
seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
if (ip_rev == EMIF_4D) {
seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
regs->read_idle_ctrl_shdw_normal);
seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
regs->read_idle_ctrl_shdw_volt_ramp);
} else if (ip_rev == EMIF_4D5) {
seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
regs->dll_calib_ctrl_shdw_normal);
seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
regs->dll_calib_ctrl_shdw_volt_ramp);
}
if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
regs->ref_ctrl_shdw_derated);
seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
regs->sdram_tim1_shdw_derated);
seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
regs->sdram_tim3_shdw_derated);
}
}
static int emif_regdump_show(struct seq_file *s, void *unused)
{
struct emif_data *emif = s->private;
struct emif_regs **regs_cache;
int i;
if (emif->duplicate)
regs_cache = emif1->regs_cache;
else
regs_cache = emif->regs_cache;
for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
do_emif_regdump_show(s, emif, regs_cache[i]);
seq_putc(s, '\n');
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(emif_regdump);
static int emif_mr4_show(struct seq_file *s, void *unused)
{
struct emif_data *emif = s->private;
seq_printf(s, "MR4=%d\n", emif->temperature_level);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(emif_mr4);
static void emif_debugfs_init(struct emif_data *emif)
{
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
Annotation
- Immediate include surface: `linux/cleanup.h`, `linux/err.h`, `linux/kernel.h`, `linux/reboot.h`, `linux/platform_data/emif_plat.h`, `linux/io.h`, `linux/device.h`, `linux/platform_device.h`.
- Detected declarations: `struct emif_data`, `function do_emif_regdump_show`, `function emif_regdump_show`, `function emif_mr4_show`, `function emif_debugfs_init`, `function emif_debugfs_exit`, `function get_emif_bus_width`, `function set_lpmode`, `function do_freq_update`, `function list_for_each_entry`.
- Atlas domain: Driver Families / drivers/memory.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.