drivers/memory/samsung/exynos5422-dmc.c

Source file repositories/reference/linux-study-clean/drivers/memory/samsung/exynos5422-dmc.c

File Facts

System
Linux kernel
Corpus path
drivers/memory/samsung/exynos5422-dmc.c
Extension
.c
Size
47704 bytes
Lines
1584
Domain
Driver Families
Bucket
drivers/memory
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dmc_opp_table {
	u32 freq_hz;
	u32 volt_uv;
};

/**
 * struct exynos5_dmc - main structure describing DMC device
 * @dev:		DMC device
 * @df:			devfreq device structure returned by devfreq framework
 * @gov_data:		configuration of devfreq governor
 * @base_drexi0:	DREX0 registers mapping
 * @base_drexi1:	DREX1 registers mapping
 * @clk_regmap:		regmap for clock controller registers
 * @lock:		protects curr_rate and frequency/voltage setting section
 * @curr_rate:		current frequency
 * @curr_volt:		current voltage
 * @opp:		OPP table
 * @opp_count:		number of 'opp' elements
 * @timings_arr_size:	number of 'timings' elements
 * @timing_row:		values for timing row register, for each OPP
 * @timing_data:	values for timing data register, for each OPP
 * @timing_power:	balues for timing power register, for each OPP
 * @timings:		DDR memory timings, from device tree
 * @min_tck:		DDR memory minimum timing values, from device tree
 * @bypass_timing_row:	value for timing row register for bypass timings
 * @bypass_timing_data:	value for timing data register for bypass timings
 * @bypass_timing_power:	value for timing power register for bypass
 *				timings
 * @vdd_mif:		Memory interface regulator
 * @fout_spll:		clock: SPLL
 * @fout_bpll:		clock: BPLL
 * @mout_spll:		clock: mux SPLL
 * @mout_bpll:		clock: mux BPLL
 * @mout_mclk_cdrex:	clock: mux mclk_cdrex
 * @mout_mx_mspll_ccore:	clock: mux mx_mspll_ccore
 * @counter:		devfreq events
 * @num_counters:	number of 'counter' elements
 * @last_overflow_ts:	time (in ns) of last overflow of each DREX
 * @load:		utilization in percents
 * @total:		total time between devfreq events
 * @in_irq_mode:	whether running in interrupt mode (true)
 *			or polling (false)
 *
 * The main structure for the Dynamic Memory Controller which covers clocks,
 * memory regions, HW information, parameters and current operating mode.
 */
struct exynos5_dmc {
	struct device *dev;
	struct devfreq *df;
	struct devfreq_simple_ondemand_data gov_data;
	void __iomem *base_drexi0;
	void __iomem *base_drexi1;
	struct regmap *clk_regmap;
	/* Protects curr_rate and frequency/voltage setting section */
	struct mutex lock;
	unsigned long curr_rate;
	unsigned long curr_volt;
	struct dmc_opp_table *opp;
	int opp_count;
	u32 timings_arr_size;
	u32 *timing_row;
	u32 *timing_data;
	u32 *timing_power;
	const struct lpddr3_timings *timings;
	const struct lpddr3_min_tck *min_tck;
	u32 bypass_timing_row;
	u32 bypass_timing_data;
	u32 bypass_timing_power;
	struct regulator *vdd_mif;
	struct clk *fout_spll;
	struct clk *fout_bpll;
	struct clk *mout_spll;
	struct clk *mout_bpll;
	struct clk *mout_mclk_cdrex;
	struct clk *mout_mx_mspll_ccore;
	struct devfreq_event_dev **counter;
	int num_counters;
	u64 last_overflow_ts[2];
	unsigned long load;
	unsigned long total;
	bool in_irq_mode;
};

#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
	{ .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }

#define TIMING_VAL2REG(timing, t_val)			\
({							\
		u32 __val;				\
		__val = (t_val) << (timing)->bit_beg;	\

Annotation

Implementation Notes