drivers/memory/tegra/mc.h

Source file repositories/reference/linux-study-clean/drivers/memory/tegra/mc.h

File Facts

System
Linux kernel
Corpus path
drivers/memory/tegra/mc.h
Extension
.h
Size
8707 bytes
Lines
286
Domain
Driver Families
Bucket
drivers/memory
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef MEMORY_TEGRA_MC_H
#define MEMORY_TEGRA_MC_H

#include <linux/bits.h>
#include <linux/io.h>
#include <linux/types.h>

#include <soc/tegra/mc.h>

#define MC_INTSTATUS					0x00
/* Bit field of MC_INTSTATUS register */
#define MC_INT_DECERR_EMEM				BIT(6)
#define MC_INT_INVALID_GART_PAGE			BIT(7)
#define MC_INT_SECURITY_VIOLATION			BIT(8)
#define MC_INT_ARBITRATION_EMEM				BIT(9)
#define MC_INT_INVALID_SMMU_PAGE			BIT(10)
#define MC_INT_INVALID_APB_ASID_UPDATE			BIT(11)
#define MC_INT_DECERR_VPR				BIT(12)
#define MC_INT_SECERR_SEC				BIT(13)
#define MC_INT_DECERR_MTS				BIT(16)
#define MC_INT_DECERR_GENERALIZED_CARVEOUT		BIT(17)
#define MC_INT_DECERR_ROUTE_SANITY			BIT(20)
#define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI		BIT(21)

#define MC_INTMASK					0x04
#define MC_GART_ERROR_REQ				0x30
#define MC_EMEM_ADR_CFG					0x54
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV			BIT(0)

#define MC_DECERR_EMEM_OTHERS_STATUS			0x58
#define MC_SECURITY_VIOLATION_STATUS			0x74
#define MC_EMEM_ARB_CFG					0x90
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)		((x) & 0x1ff)
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK		0x1ff

#define MC_EMEM_ARB_OUTSTANDING_REQ			0x94
#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE	BIT(30)
#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE	BIT(31)
#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK		0x1ff

#define MC_EMEM_ARB_TIMING_RCD				0x98
#define MC_EMEM_ARB_TIMING_RP				0x9c
#define MC_EMEM_ARB_TIMING_RC				0xa0
#define MC_EMEM_ARB_TIMING_RAS				0xa4
#define MC_EMEM_ARB_TIMING_FAW				0xa8
#define MC_EMEM_ARB_TIMING_RRD				0xac
#define MC_EMEM_ARB_TIMING_RAP2PRE			0xb0
#define MC_EMEM_ARB_TIMING_WAP2PRE			0xb4
#define MC_EMEM_ARB_TIMING_R2R				0xb8
#define MC_EMEM_ARB_TIMING_W2W				0xbc
#define MC_EMEM_ARB_TIMING_R2W				0xc0
#define MC_EMEM_ARB_TIMING_W2R				0xc4
#define MC_EMEM_ARB_MISC2				0xc8
#define MC_EMEM_ARB_DA_TURNS				0xd0
#define MC_EMEM_ARB_DA_COVERS				0xd4
#define MC_EMEM_ARB_MISC0				0xd8
#define MC_EMEM_ARB_MISC1				0xdc
#define MC_EMEM_ARB_RING1_THROTTLE			0xe0
#define MC_EMEM_ARB_OVERRIDE				0xe8
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK			0x3

#define MC_TIMING_CONTROL_DBG				0xf8
#define MC_TIMING_CONTROL				0xfc
#define MC_TIMING_UPDATE				BIT(0)

#define MC_GLOBAL_INTSTATUS				0xf24

/* Bit field of MC_ERR_STATUS_0 register */
#define MC_ERR_STATUS_RW				BIT(16)
#define MC_ERR_STATUS_SECURITY				BIT(17)
#define MC_ERR_STATUS_NONSECURE				BIT(25)
#define MC_ERR_STATUS_WRITABLE				BIT(26)
#define MC_ERR_STATUS_READABLE				BIT(27)

#define MC_ERR_STATUS_GSC_ADR_HI_MASK			0xffff
#define MC_ERR_STATUS_GSC_ADR_HI_SHIFT			16
#define MC_ERR_STATUS_RT_ADR_HI_SHIFT			15

#define MC_ERR_STATUS_TYPE_SHIFT			28
#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE		(0x6 << 28)
#define MC_ERR_STATUS_RT_TYPE_MASK			(0xf << 28)
#define MC_ERR_STATUS_RT_TYPE_SHIFT			28

#define MC_ERR_STATUS_ADR_HI_SHIFT			20

#define MC_BROADCAST_CHANNEL				~0

/* Tegra264 specific registers */

/* Registers for MSS HUB */

Annotation

Implementation Notes