drivers/memory/tegra/tegra194.c
Source file repositories/reference/linux-study-clean/drivers/memory/tegra/tegra194.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/memory/tegra/tegra194.c- Extension
.c- Size
- 24616 bytes
- Lines
- 1374
- Domain
- Driver Families
- Bucket
- drivers/memory
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
soc/tegra/mc.hdt-bindings/memory/tegra194-mc.hmc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
*/
#include <soc/tegra/mc.h>
#include <dt-bindings/memory/tegra194-mc.h>
#include "mc.h"
static const struct tegra_mc_client tegra194_mc_clients[] = {
{
.id = TEGRA194_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x000,
.security = 0x004,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU7R,
.name = "miu7r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x008,
.security = 0x00c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU7W,
.name = "miu7w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x010,
.security = 0x014,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA194_SID_HDA,
.regs = {
.sid = {
.override = 0x0a8,
.security = 0x0ac,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA194_SID_HOST1X,
.regs = {
.sid = {
.override = 0x0b0,
.security = 0x0b4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA194_SID_NVENC,
.regs = {
.sid = {
.override = 0x0e0,
.security = 0x0e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA194_SID_SATA,
.regs = {
.sid = {
.override = 0x0f8,
.security = 0x0fc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x138,
.security = 0x13c,
Annotation
- Immediate include surface: `soc/tegra/mc.h`, `dt-bindings/memory/tegra194-mc.h`, `mc.h`.
- Atlas domain: Driver Families / drivers/memory.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.