drivers/memory/tegra/tegra20-emc.c
Source file repositories/reference/linux-study-clean/drivers/memory/tegra/tegra20-emc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/memory/tegra/tegra20-emc.c- Extension
.c- Size
- 29036 bytes
- Lines
- 1171
- Domain
- Driver Families
- Bucket
- drivers/memory
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk.hlinux/clk/tegra.hlinux/debugfs.hlinux/devfreq.hlinux/err.hlinux/interconnect-provider.hlinux/interrupt.hlinux/io.hlinux/iopoll.hlinux/kernel.hlinux/module.hlinux/mutex.hlinux/of.hlinux/platform_device.hlinux/pm_opp.hlinux/slab.hlinux/sort.hlinux/types.hsoc/tegra/common.hsoc/tegra/fuse.h../jedec_ddr.h../of_memory.hmc.htegra-emc-common.h
Detected Declarations
struct emc_timingstruct tegra_emcenum emc_dram_typefunction tegra20_emc_isrfunction emc_prepare_timing_changefunction emc_complete_timing_changefunction tegra20_emc_clk_change_notifyfunction load_one_timing_from_dtfunction cmp_timingsfunction tegra20_emc_load_timings_from_dtfunction for_each_child_of_node_scopedfunction tegra20_emc_find_node_by_ram_codefunction for_each_child_of_nodefunction emc_read_lpddr_mode_registerfunction emc_read_lpddr_sdram_infofunction emc_setup_hwfunction emc_round_ratefunction tegra20_emc_validate_ratefunction tegra20_emc_debug_available_rates_showfunction tegra20_emc_debug_min_rate_getfunction tegra20_emc_debug_min_rate_setfunction tegra20_emc_debug_max_rate_getfunction tegra20_emc_debug_max_rate_setfunction tegra20_emc_debugfs_initfunction to_tegra_emc_providerfunction emc_of_icc_xlate_extendedfunction emc_icc_setfunction tegra20_emc_interconnect_initfunction devm_tegra20_emc_unset_callbackfunction devm_tegra20_emc_unreg_clk_notifierfunction tegra20_emc_init_clkfunction tegra20_emc_devfreq_targetfunction tegra20_emc_devfreq_get_dev_statusfunction tegra20_emc_devfreq_initfunction tegra20_emc_probe
Annotated Snippet
struct emc_timing {
unsigned long rate;
u32 data[ARRAY_SIZE(emc_timing_registers)];
};
struct tegra_emc {
struct device *dev;
struct tegra_mc *mc;
struct icc_provider provider;
struct notifier_block clk_nb;
struct clk *clk;
void __iomem *regs;
unsigned int dram_bus_width;
struct emc_timing *timings;
unsigned int num_timings;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
struct tegra_emc_rate_requests reqs;
struct devfreq_simple_ondemand_data ondemand_data;
/* memory chip identity information */
union lpddr2_basic_config4 basic_conf4;
unsigned int manufacturer_id;
unsigned int revision_id1;
unsigned int revision_id2;
bool mrr_error;
};
static irqreturn_t tegra20_emc_isr(int irq, void *data)
{
struct tegra_emc *emc = data;
u32 intmask = EMC_REFRESH_OVERFLOW_INT;
u32 status;
status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
if (!status)
return IRQ_NONE;
/* notify about HW problem */
if (status & EMC_REFRESH_OVERFLOW_INT)
dev_err_ratelimited(emc->dev,
"refresh request overflow timeout\n");
/* clear interrupts */
writel_relaxed(status, emc->regs + EMC_INTSTATUS);
return IRQ_HANDLED;
}
static struct emc_timing *tegra20_emc_find_timing(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = NULL;
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate >= rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu\n", rate);
return NULL;
}
return timing;
}
static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
{
struct emc_timing *timing = tegra20_emc_find_timing(emc, rate);
unsigned int i;
if (!timing)
return -EINVAL;
dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
__func__, timing->rate, rate);
/* program shadow registers */
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/clk/tegra.h`, `linux/debugfs.h`, `linux/devfreq.h`, `linux/err.h`, `linux/interconnect-provider.h`, `linux/interrupt.h`.
- Detected declarations: `struct emc_timing`, `struct tegra_emc`, `enum emc_dram_type`, `function tegra20_emc_isr`, `function emc_prepare_timing_change`, `function emc_complete_timing_change`, `function tegra20_emc_clk_change_notify`, `function load_one_timing_from_dt`, `function cmp_timings`, `function tegra20_emc_load_timings_from_dt`.
- Atlas domain: Driver Families / drivers/memory.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.