drivers/memory/tegra/tegra210-emc.h

Source file repositories/reference/linux-study-clean/drivers/memory/tegra/tegra210-emc.h

File Facts

System
Linux kernel
Corpus path
drivers/memory/tegra/tegra210-emc.h
Extension
.h
Size
39849 bytes
Lines
1017
Domain
Driver Families
Bucket
drivers/memory
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct tegra210_emc_per_channel_regs {
	u16 bank;
	u16 offset;
};

struct tegra210_emc_table_register_offsets {
	u16 burst[BURST_REGS_SIZE];
	u16 trim[TRIM_REGS_SIZE];
	u16 burst_mc[BURST_MC_REGS_SIZE];
	u16 la_scale[BURST_UP_DOWN_REGS_SIZE];
	struct tegra210_emc_per_channel_regs burst_per_channel[BURST_REGS_PER_CHANNEL_SIZE];
	struct tegra210_emc_per_channel_regs trim_per_channel[TRIM_REGS_PER_CHANNEL_SIZE];
	struct tegra210_emc_per_channel_regs vref_per_channel[VREF_REGS_PER_CHANNEL_SIZE];
};

struct tegra210_emc_timing {
	u32 revision;
	const char dvfs_ver[60];
	u32 rate;
	u32 min_volt;
	u32 gpu_min_volt;
	const char clock_src[32];
	u32 clk_src_emc;
	u32 needs_training;
	u32 training_pattern;
	u32 trained;

	u32 periodic_training;
	u32 trained_dram_clktree[DRAM_CLKTREE_NUM];
	u32 current_dram_clktree[DRAM_CLKTREE_NUM];
	u32 run_clocks;
	u32 tree_margin;

	u32 num_burst;
	u32 num_burst_per_ch;
	u32 num_trim;
	u32 num_trim_per_ch;
	u32 num_mc_regs;
	u32 num_up_down;
	u32 vref_num;
	u32 training_mod_num;
	u32 dram_timing_num;

	u32 ptfv_list[PTFV_ARRAY_SIZE];

	u32 burst_regs[BURST_REGS_SIZE];
	u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE];
	u32 shadow_regs_ca_train[BURST_REGS_SIZE];
	u32 shadow_regs_quse_train[BURST_REGS_SIZE];
	u32 shadow_regs_rdwr_train[BURST_REGS_SIZE];

	u32 trim_regs[TRIM_REGS_SIZE];
	u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE];

	u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE];

	u32 dram_timings[DRAM_TIMINGS_NUM];
	u32 training_mod_regs[TRAINING_MOD_REGS_SIZE];
	u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE];
	u32 burst_mc_regs[BURST_MC_REGS_SIZE];
	u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE];

	u32 min_mrs_wait;
	u32 emc_mrw;
	u32 emc_mrw2;
	u32 emc_mrw3;
	u32 emc_mrw4;
	u32 emc_mrw9;
	u32 emc_mrs;
	u32 emc_emrs;
	u32 emc_emrs2;
	u32 emc_auto_cal_config;
	u32 emc_auto_cal_config2;
	u32 emc_auto_cal_config3;
	u32 emc_auto_cal_config4;
	u32 emc_auto_cal_config5;
	u32 emc_auto_cal_config6;
	u32 emc_auto_cal_config7;
	u32 emc_auto_cal_config8;
	u32 emc_cfg_2;
	u32 emc_sel_dpd_ctrl;
	u32 emc_fdpd_ctrl_cmd_no_ramp;
	u32 dll_clk_src;
	u32 clk_out_enb_x_0_clk_enb_emc_dll;
	u32 latency;
};

enum tegra210_emc_refresh {
	TEGRA210_EMC_REFRESH_NOMINAL = 0,
	TEGRA210_EMC_REFRESH_2X,

Annotation

Implementation Notes