drivers/memory/ti-emif-sram-pm.S

Source file repositories/reference/linux-study-clean/drivers/memory/ti-emif-sram-pm.S

File Facts

System
Linux kernel
Corpus path
drivers/memory/ti-emif-sram-pm.S
Extension
.S
Size
10919 bytes
Lines
369
Domain
Driver Families
Bucket
drivers/memory
Inferred role
Driver Families: drivers/memory
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/page.h>

#include "emif.h"
#include "ti-emif-asm-offsets.h"

#define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES	0x00a0
#define EMIF_POWER_MGMT_SR_TIMER_MASK			0x00f0
#define EMIF_POWER_MGMT_SELF_REFRESH_MODE		0x0200
#define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK		0x0700

#define EMIF_SDCFG_TYPE_DDR2				0x2 << SDRAM_TYPE_SHIFT
#define EMIF_SDCFG_TYPE_DDR3				0x3 << SDRAM_TYPE_SHIFT
#define EMIF_STATUS_READY				0x4

#define AM43XX_EMIF_PHY_CTRL_REG_COUNT                  0x120

#define EMIF_AM437X_REGISTERS				0x1

	.arm
	.align 3
	.arch armv7-a

ENTRY(ti_emif_sram)

/*
 * void ti_emif_save_context(void)
 *
 * Used during suspend to save the context of all required EMIF registers
 * to local memory if the EMIF is going to lose context during the sleep
 * transition. Operates on the VIRTUAL address of the EMIF.
 */
ENTRY(ti_emif_save_context)
	stmfd   sp!, {r4 - r11, lr}     @ save registers on stack

	adr	r4, ti_emif_pm_sram_data
	ldr	r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
	ldr	r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]

	/* Save EMIF configuration */
	ldr	r1, [r0, #EMIF_SDRAM_CONFIG]
	str	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
	str	r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_SDRAM_TIMING_1]
	str     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_SDRAM_TIMING_2]
	str     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_SDRAM_TIMING_3]
	str     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
	str     r1, [r2, #EMIF_PMCR_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
	str     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
	str     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]

	ldr	r1, [r0, #EMIF_DDR_PHY_CTRL_1]
	str     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]

	ldr	r1, [r0, #EMIF_COS_CONFIG]
	str     r1, [r2, #EMIF_COS_CONFIG_OFFSET]

Annotation

Implementation Notes