drivers/mfd/cs47l24-tables.c

Source file repositories/reference/linux-study-clean/drivers/mfd/cs47l24-tables.c

File Facts

System
Linux kernel
Corpus path
drivers/mfd/cs47l24-tables.c
Extension
.c
Size
71949 bytes
Lines
1625
Domain
Driver Families
Bucket
drivers/mfd
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Data tables for CS47L24 codec
 *
 * Copyright 2015 Cirrus Logic, Inc.
 *
 * Author: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
 */

#include <linux/module.h>

#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <linux/device.h>

#include "arizona.h"

#define CS47L24_NUM_ISR 5

static const struct reg_sequence cs47l24_reva_patch[] = {
	{ 0x80,  0x3 },
	{ 0x27C, 0x0010 },
	{ 0x221, 0x0070 },
	{ 0x80,  0x0 },
};

int cs47l24_patch(struct arizona *arizona)
{
	return regmap_register_patch(arizona->regmap,
				     cs47l24_reva_patch,
				     ARRAY_SIZE(cs47l24_reva_patch));
}
EXPORT_SYMBOL_GPL(cs47l24_patch);

static const struct regmap_irq cs47l24_irqs[ARIZONA_NUM_IRQ] = {
	[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
	[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

	[ARIZONA_IRQ_DSP3_RAM_RDY] = {
		.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
	},
	[ARIZONA_IRQ_DSP2_RAM_RDY] = {
		.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ8] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ7] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ6] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ5] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ4] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ3] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ2] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
	},
	[ARIZONA_IRQ_DSP_IRQ1] = {
		.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
	},

	[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
		.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
	},
	[ARIZONA_IRQ_SPK_OVERHEAT] = {
		.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
	},
	[ARIZONA_IRQ_WSEQ_DONE] = {
		.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
	},
	[ARIZONA_IRQ_DRC2_SIG_DET] = {
		.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
	},
	[ARIZONA_IRQ_DRC1_SIG_DET] = {
		.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
	},
	[ARIZONA_IRQ_ASRC2_LOCK] = {
		.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
	},
	[ARIZONA_IRQ_ASRC1_LOCK] = {
		.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
	},

Annotation

Implementation Notes