drivers/mfd/exynos-lpass.c
Source file repositories/reference/linux-study-clean/drivers/mfd/exynos-lpass.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mfd/exynos-lpass.c- Extension
.c- Size
- 5235 bytes
- Lines
- 196
- Domain
- Driver Families
- Bucket
- drivers/mfd
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/delay.hlinux/io.hlinux/module.hlinux/of.hlinux/of_platform.hlinux/platform_device.hlinux/pm_runtime.hlinux/regmap.hlinux/soc/samsung/exynos-regs-pmu.hlinux/types.h
Detected Declarations
struct exynos_lpassfunction exynos_lpass_core_sw_resetfunction exynos_lpass_enablefunction exynos_lpass_disablefunction exynos_lpass_disable_lpassfunction exynos_lpass_probefunction exynos_lpass_suspendfunction exynos_lpass_resume
Annotated Snippet
struct exynos_lpass {
/* pointer to the LPASS TOP regmap */
struct regmap *top;
struct clk *sfr0_clk;
};
static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
{
unsigned int val = 0;
regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
val &= ~mask;
regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
usleep_range(100, 150);
val |= mask;
regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
}
static void exynos_lpass_enable(struct exynos_lpass *lpass)
{
clk_prepare_enable(lpass->sfr0_clk);
/* Unmask SFR, DMA and I2S interrupt */
regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
LPASS_INTR_UART);
exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
}
static void exynos_lpass_disable(struct exynos_lpass *lpass)
{
/* Mask any unmasked IP interrupt sources */
regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
clk_disable_unprepare(lpass->sfr0_clk);
}
static const struct regmap_config exynos_lpass_reg_conf = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xfc,
};
static void exynos_lpass_disable_lpass(void *data)
{
struct platform_device *pdev = data;
struct exynos_lpass *lpass = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
exynos_lpass_disable(lpass);
}
static int exynos_lpass_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct exynos_lpass *lpass;
void __iomem *base_top;
int ret;
lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
if (!lpass)
return -ENOMEM;
base_top = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base_top))
return PTR_ERR(base_top);
lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
if (IS_ERR(lpass->sfr0_clk))
return PTR_ERR(lpass->sfr0_clk);
lpass->top = devm_regmap_init_mmio(dev, base_top,
&exynos_lpass_reg_conf);
if (IS_ERR(lpass->top)) {
dev_err(dev, "LPASS top regmap initialization failed\n");
return PTR_ERR(lpass->top);
}
Annotation
- Immediate include surface: `linux/clk.h`, `linux/delay.h`, `linux/io.h`, `linux/module.h`, `linux/of.h`, `linux/of_platform.h`, `linux/platform_device.h`, `linux/pm_runtime.h`.
- Detected declarations: `struct exynos_lpass`, `function exynos_lpass_core_sw_reset`, `function exynos_lpass_enable`, `function exynos_lpass_disable`, `function exynos_lpass_disable_lpass`, `function exynos_lpass_probe`, `function exynos_lpass_suspend`, `function exynos_lpass_resume`.
- Atlas domain: Driver Families / drivers/mfd.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.