drivers/mfd/intel_pmc_bxt.c

Source file repositories/reference/linux-study-clean/drivers/mfd/intel_pmc_bxt.c

File Facts

System
Linux kernel
Corpus path
drivers/mfd/intel_pmc_bxt.c
Extension
.c
Size
12280 bytes
Lines
468
Domain
Driver Families
Bucket
drivers/mfd
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for the Intel Broxton PMC
 *
 * (C) Copyright 2014 - 2020 Intel Corporation
 *
 * This driver is based on Intel SCU IPC driver (intel_scu_ipc.c) by
 * Sreedhara DS <sreedhara.ds@intel.com>
 *
 * The PMC (Power Management Controller) running on the ARC processor
 * communicates with another entity running in the IA (Intel Architecture)
 * core through an IPC (Intel Processor Communications) mechanism which in
 * turn sends messages between the IA and the PMC.
 */

#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_pmc_bxt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/platform_data/itco_wdt.h>
#include <linux/platform_data/x86/intel_scu_ipc.h>

/* Residency with clock rate at 19.2MHz to usecs */
#define S0IX_RESIDENCY_IN_USECS(d, s)		\
({						\
	u64 result = 10ull * ((d) + (s));	\
	do_div(result, 192);			\
	result;					\
})

/* Resources exported from IFWI */
#define PLAT_RESOURCE_IPC_INDEX		0
#define PLAT_RESOURCE_IPC_SIZE		0x1000
#define PLAT_RESOURCE_GCR_OFFSET	0x1000
#define PLAT_RESOURCE_GCR_SIZE		0x1000
#define PLAT_RESOURCE_BIOS_DATA_INDEX	1
#define PLAT_RESOURCE_BIOS_IFACE_INDEX	2
#define PLAT_RESOURCE_TELEM_SSRAM_INDEX	3
#define PLAT_RESOURCE_ISP_DATA_INDEX	4
#define PLAT_RESOURCE_ISP_IFACE_INDEX	5
#define PLAT_RESOURCE_GTD_DATA_INDEX	6
#define PLAT_RESOURCE_GTD_IFACE_INDEX	7
#define PLAT_RESOURCE_ACPI_IO_INDEX	0

/*
 * BIOS does not create an ACPI device for each PMC function, but
 * exports multiple resources from one ACPI device (IPC) for multiple
 * functions. This driver is responsible for creating a child device and
 * to export resources for those functions.
 */
#define SMI_EN_OFFSET			0x0040
#define SMI_EN_SIZE			4
#define TCO_BASE_OFFSET			0x0060
#define TCO_REGS_SIZE			16
#define TELEM_SSRAM_SIZE		240
#define TELEM_PMC_SSRAM_OFFSET		0x1b00
#define TELEM_PUNIT_SSRAM_OFFSET	0x1a00

/* Commands */
#define PMC_NORTHPEAK_CTRL		0xed

static inline bool is_gcr_valid(u32 offset)
{
	return offset < PLAT_RESOURCE_GCR_SIZE - 8;
}

/**
 * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
 * @pmc: PMC device pointer
 * @offset: offset of GCR register from GCR address base
 * @data: data pointer for storing the register output
 *
 * Reads the 64-bit PMC GCR register at given offset.
 *
 * Return: Negative value on error or 0 on success.
 */
int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data)
{
	if (!is_gcr_valid(offset))
		return -EINVAL;

	spin_lock(&pmc->gcr_lock);
	*data = readq(pmc->gcr_mem_base + offset);
	spin_unlock(&pmc->gcr_lock);

Annotation

Implementation Notes