drivers/mfd/intel_soc_pmic_bxtwc.c

Source file repositories/reference/linux-study-clean/drivers/mfd/intel_soc_pmic_bxtwc.c

File Facts

System
Linux kernel
Corpus path
drivers/mfd/intel_soc_pmic_bxtwc.c
Extension
.c
Size
15927 bytes
Lines
631
Domain
Driver Families
Bucket
drivers/mfd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * MFD core driver for Intel Broxton Whiskey Cove PMIC
 *
 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
 */

#include <linux/acpi.h>
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gfp_types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kstrtox.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_bxtwc.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_data/x86/intel_scu_ipc.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/types.h>

/* PMIC device registers */
#define REG_ADDR_MASK		GENMASK(15, 8)
#define REG_ADDR_SHIFT		8
#define REG_OFFSET_MASK		GENMASK(7, 0)

/* Interrupt Status Registers */
#define BXTWC_IRQLVL1		0x4E02

#define BXTWC_PWRBTNIRQ		0x4E03
#define BXTWC_THRM0IRQ		0x4E04
#define BXTWC_THRM1IRQ		0x4E05
#define BXTWC_THRM2IRQ		0x4E06
#define BXTWC_BCUIRQ		0x4E07
#define BXTWC_ADCIRQ		0x4E08
#define BXTWC_CHGR0IRQ		0x4E09
#define BXTWC_CHGR1IRQ		0x4E0A
#define BXTWC_GPIOIRQ0		0x4E0B
#define BXTWC_GPIOIRQ1		0x4E0C
#define BXTWC_CRITIRQ		0x4E0D
#define BXTWC_TMUIRQ		0x4FB6

/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1		0x4E0E
#define BXTWC_MIRQLVL1_MCHGR	BIT(5)

#define BXTWC_MPWRBTNIRQ	0x4E0F
#define BXTWC_MTHRM0IRQ		0x4E12
#define BXTWC_MTHRM1IRQ		0x4E13
#define BXTWC_MTHRM2IRQ		0x4E14
#define BXTWC_MBCUIRQ		0x4E15
#define BXTWC_MADCIRQ		0x4E16
#define BXTWC_MCHGR0IRQ		0x4E17
#define BXTWC_MCHGR1IRQ		0x4E18
#define BXTWC_MGPIO0IRQ		0x4E19
#define BXTWC_MGPIO1IRQ		0x4E1A
#define BXTWC_MCRITIRQ		0x4E1B
#define BXTWC_MTMUIRQ		0x4FB7

/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV	4

#define PMC_PMIC_ACCESS		0xFF
#define PMC_PMIC_READ		0x0
#define PMC_PMIC_WRITE		0x1

enum bxtwc_irqs {
	BXTWC_PWRBTN_LVL1_IRQ = 0,
	BXTWC_TMU_LVL1_IRQ,
	BXTWC_THRM_LVL1_IRQ,
	BXTWC_BCU_LVL1_IRQ,
	BXTWC_ADC_LVL1_IRQ,
	BXTWC_CHGR_LVL1_IRQ,
	BXTWC_GPIO_LVL1_IRQ,
	BXTWC_CRIT_LVL1_IRQ,
};

enum bxtwc_irqs_pwrbtn {
	BXTWC_PWRBTN_IRQ = 0,
	BXTWC_UIBTN_IRQ,
};

Annotation

Implementation Notes