drivers/mfd/intel_soc_pmic_mrfld.c

Source file repositories/reference/linux-study-clean/drivers/mfd/intel_soc_pmic_mrfld.c

File Facts

System
Linux kernel
Corpus path
drivers/mfd/intel_soc_pmic_mrfld.c
Extension
.c
Size
3801 bytes
Lines
158
Domain
Driver Families
Bucket
drivers/mfd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device access for Basin Cove PMIC
 *
 * Copyright (c) 2019, Intel Corporation.
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 */

#include <linux/acpi.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_mrfld.h>
#include <linux/module.h>
#include <linux/platform_data/x86/intel_scu_ipc.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

/*
 * Level 2 IRQs
 *
 * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
 * without an assistance. Thus, each of the Level 1 IRQ is represented
 * as a separate RTE in IOAPIC.
 */
static struct resource irq_level2_resources[] = {
	DEFINE_RES_IRQ(0), /* power button */
	DEFINE_RES_IRQ(0), /* TMU */
	DEFINE_RES_IRQ(0), /* thermal */
	DEFINE_RES_IRQ(0), /* BCU */
	DEFINE_RES_IRQ(0), /* ADC */
	DEFINE_RES_IRQ(0), /* charger */
	DEFINE_RES_IRQ(0), /* GPIO */
};

static const struct mfd_cell bcove_dev[] = {
	{
		.name = "mrfld_bcove_pwrbtn",
		.num_resources = 1,
		.resources = &irq_level2_resources[0],
	}, {
		.name = "mrfld_bcove_tmu",
		.num_resources = 1,
		.resources = &irq_level2_resources[1],
	}, {
		.name = "mrfld_bcove_thermal",
		.num_resources = 1,
		.resources = &irq_level2_resources[2],
	}, {
		.name = "mrfld_bcove_bcu",
		.num_resources = 1,
		.resources = &irq_level2_resources[3],
	}, {
		.name = "mrfld_bcove_adc",
		.num_resources = 1,
		.resources = &irq_level2_resources[4],
	}, {
		.name = "mrfld_bcove_charger",
		.num_resources = 1,
		.resources = &irq_level2_resources[5],
	}, {
		.name = "mrfld_bcove_pwrsrc",
		.num_resources = 1,
		.resources = &irq_level2_resources[5],
	}, {
		.name = "mrfld_bcove_gpio",
		.num_resources = 1,
		.resources = &irq_level2_resources[6],
	},
	{	.name = "mrfld_bcove_region", },
};

static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
				    unsigned int *val)
{
	struct intel_soc_pmic *pmic = context;
	u8 ipc_out;
	int ret;

	ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out);
	if (ret)
		return ret;

	*val = ipc_out;
	return 0;
}

static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
				     unsigned int val)
{

Annotation

Implementation Notes