drivers/mfd/max77759.c
Source file repositories/reference/linux-study-clean/drivers/mfd/max77759.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mfd/max77759.c- Extension
.c- Size
- 22718 bytes
- Lines
- 740
- Domain
- Driver Families
- Bucket
- drivers/mfd
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/bitfield.hlinux/bits.hlinux/cleanup.hlinux/completion.hlinux/dev_printk.hlinux/device.hlinux/err.hlinux/i2c.hlinux/init.hlinux/interrupt.hlinux/irq.hlinux/jiffies.hlinux/mfd/core.hlinux/mfd/max77759.hlinux/mod_devicetable.hlinux/module.hlinux/mutex.hlinux/of.hlinux/overflow.hlinux/regmap.h
Detected Declarations
struct max77759_i2c_subdevenum max77759_i2c_subdev_idfunction max77759_maxq_commandfunction msecs_to_jiffiesfunction apcmdres_irq_handlerfunction max77759_create_i2c_subdevfunction max77759_add_chained_irq_chipfunction max77759_add_chained_maxqfunction max77759_add_chained_topsysfunction max77759_add_chained_chargerfunction max77759_probeexport max77759_maxq_command
Annotated Snippet
struct max77759_i2c_subdev {
enum max77759_i2c_subdev_id id;
const struct regmap_config *cfg;
u16 i2c_address;
};
static const struct regmap_range max77759_top_registers[] = {
regmap_reg_range(0x00, 0x02), /* PMIC_ID / PMIC_REVISION / OTP_REVISION */
regmap_reg_range(0x22, 0x24), /* INTSRC / INTSRCMASK / TOPSYS_INT */
regmap_reg_range(0x26, 0x26), /* TOPSYS_INT_MASK */
regmap_reg_range(0x40, 0x40), /* I2C_CNFG */
regmap_reg_range(0x50, 0x51), /* SWRESET / CONTROL_FG */
};
static const struct regmap_range max77759_top_ro_registers[] = {
regmap_reg_range(0x00, 0x02),
regmap_reg_range(0x22, 0x22),
};
static const struct regmap_range max77759_top_volatile_registers[] = {
regmap_reg_range(0x22, 0x22),
regmap_reg_range(0x24, 0x24),
};
static const struct regmap_access_table max77759_top_wr_table = {
.yes_ranges = max77759_top_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_top_registers),
.no_ranges = max77759_top_ro_registers,
.n_no_ranges = ARRAY_SIZE(max77759_top_ro_registers),
};
static const struct regmap_access_table max77759_top_rd_table = {
.yes_ranges = max77759_top_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_top_registers),
};
static const struct regmap_access_table max77759_top_volatile_table = {
.yes_ranges = max77759_top_volatile_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_top_volatile_registers),
};
static const struct regmap_config max77759_regmap_config_top = {
.name = "top",
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77759_PMIC_REG_CONTROL_FG,
.wr_table = &max77759_top_wr_table,
.rd_table = &max77759_top_rd_table,
.volatile_table = &max77759_top_volatile_table,
.num_reg_defaults_raw = MAX77759_PMIC_REG_CONTROL_FG + 1,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_range max77759_maxq_registers[] = {
regmap_reg_range(0x60, 0x73), /* Device ID, Rev, INTx, STATUSx, MASKx */
regmap_reg_range(0x81, 0xa1), /* AP_DATAOUTx */
regmap_reg_range(0xb1, 0xd1), /* AP_DATAINx */
regmap_reg_range(0xe0, 0xe0), /* UIC_SWRST */
};
static const struct regmap_range max77759_maxq_ro_registers[] = {
regmap_reg_range(0x60, 0x63), /* Device ID, Rev */
regmap_reg_range(0x68, 0x6f), /* STATUSx */
regmap_reg_range(0xb1, 0xd1),
};
static const struct regmap_range max77759_maxq_volatile_registers[] = {
regmap_reg_range(0x64, 0x6f), /* INTx, STATUSx */
regmap_reg_range(0xb1, 0xd1),
regmap_reg_range(0xe0, 0xe0),
};
static const struct regmap_access_table max77759_maxq_wr_table = {
.yes_ranges = max77759_maxq_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers),
.no_ranges = max77759_maxq_ro_registers,
.n_no_ranges = ARRAY_SIZE(max77759_maxq_ro_registers),
};
static const struct regmap_access_table max77759_maxq_rd_table = {
.yes_ranges = max77759_maxq_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers),
};
static const struct regmap_access_table max77759_maxq_volatile_table = {
.yes_ranges = max77759_maxq_volatile_registers,
.n_yes_ranges = ARRAY_SIZE(max77759_maxq_volatile_registers),
};
static const struct regmap_config max77759_regmap_config_maxq = {
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/bitfield.h`, `linux/bits.h`, `linux/cleanup.h`, `linux/completion.h`, `linux/dev_printk.h`, `linux/device.h`, `linux/err.h`.
- Detected declarations: `struct max77759_i2c_subdev`, `enum max77759_i2c_subdev_id`, `function max77759_maxq_command`, `function msecs_to_jiffies`, `function apcmdres_irq_handler`, `function max77759_create_i2c_subdev`, `function max77759_add_chained_irq_chip`, `function max77759_add_chained_maxq`, `function max77759_add_chained_topsys`, `function max77759_add_chained_charger`.
- Atlas domain: Driver Families / drivers/mfd.
- Implementation status: integration implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.